Article

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization

Authors:

Sandeep Kumar Goel,

Erik Jan MarinissenAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 10738

Published: 03 March 2003 Publication History

Abstract

This paper extends existing SOC test architecture design approaches that minimize required tester vector memory depth and test application time, with the capability to minimize the wire length required by the test architecture. We present a simple, yet effective wire length cost model for test architectures together with a new test architecture design algorithm that minimizes both test time and wire length. The user specifies the relative weight of the costs of test time versus wire length. In an integrated fashion, the algorithm partitions the total available TAM width over individual TAMs, assigns the modules to these TAMs, and orders the modules within one TAM such that the total cost is minimized. Experimental results on five benchmark SOCs show that we can obtain savings of up to 86% in wiring costs at the expense of > 4% in test time.

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Cited By

Amory ALazzari CLubaszewski MMoraes FCavalcanti AMelcher EBecker J(2011)Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCsProceedings of the 24th symposium on Integrated circuits and systems design10.1145/2020876.2020894(73-78)Online publication date: 30-Aug-2011
https://dl.acm.org/doi/10.1145/2020876.2020894
Jiang LHuang LXu QBenini LDe Micheli GAl-Hashimi BMueller W(2009)Test architecture design and optimization for three-dimensional SoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874672(220-225)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874672
Jiang LXu QChakrabarty KMak TRoychowdhury J(2009)Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraintProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687434(191-196)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687434
Show More Cited By

Index Terms

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
1. Hardware

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cover image ACM Conferences

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

Publication History

Published: 03 March 2003

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DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Citations

Cited By

Amory ALazzari CLubaszewski MMoraes FCavalcanti AMelcher EBecker J(2011)Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCsProceedings of the 24th symposium on Integrated circuits and systems design10.1145/2020876.2020894(73-78)Online publication date: 30-Aug-2011
https://dl.acm.org/doi/10.1145/2020876.2020894
Jiang LHuang LXu QBenini LDe Micheli GAl-Hashimi BMueller W(2009)Test architecture design and optimization for three-dimensional SoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874672(220-225)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874672
Jiang LXu QChakrabarty KMak TRoychowdhury J(2009)Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraintProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687434(191-196)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687434
Xu QNicolici N(2006)DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCsIEEE Transactions on Computers10.1109/TC.2006.5655:4(470-485)Online publication date: 1-Apr-2006
https://dl.acm.org/doi/10.1109/TC.2006.56
Goel SChiu KMarinissen ENguyen TOostdijk S(2004)Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System ChipProceedings of the conference on Design, automation and test in Europe - Volume 310.5555/968880.969238Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968880.969238
Cota ÉCarro LLubaszewski MOrailoğlu A(2004)Searching for Global Test Costs Optimization in Core-Based SystemsJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000039604.64927.0f20:4(357-373)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000039604.64927.0f

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