Article

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network

Authors:

Adrijean Adriahantenaina,

Herve Charlery,

Alain Greiner,

Laurent Mortiez, and

Cesar Albenes ZeferinoAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

March 2003

Page 20070

Published: 03 March 2003 Publication History

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Abstract

This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators (masters) and targets (slaves). Performance comparisons between a classical PI-bus based interconnect and the SPIN micro-network are analyzed.

References

[1]

{1} L. Benini, G. De Micheli, «Networks on Chips: A New SoC Paradigm», IEEE Computer, Jan. 2002, pp.70-78.

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Google Scholar

[2]

{2} P. Guerrier, A. Greiner, "A generic architecture for on-chip packet-switched interconnections, DATE'2000.

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Google Scholar

[3]

{3} Siemens, OMI 324: PI-Bus - Ver.0.3d. Munich, Siemens AG, 1994.

Google Scholar

[4]

{4} IBM CoreConnect Bus Architecure, http://www- 3.ibm.com/chips/products/coreconnect/index.html

Google Scholar

[5]

{5} W. J. Dally and B. Towles, «Route Packets, Not Wires: On-Chip Interconnection Networks», DAC'2001.

Digital Library

Google Scholar

[6]

{6} Virtual Socket Interface Alliance, Virtual Component Interface Standard, OCB 2.1.0, March 2000.

Google Scholar

[7]

{7} Pétrot Frédéric, Hommais Denis, Greiner Alain, "A Simulation Environment for Core Based Embedded Systems" Proceeding of the 30th Annual Simulation Symposium, Atlanta, Georgia, April 1997, pp. 86-91.

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Balfour JDally W(2014)Design tradeoffs for tiled CMP on-chip networksACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667187(390-401)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667187
Chen CPark SKrishna TSubramanian SChandrakasan APeh LMacii E(2013)SMARTProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485371(338-343)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485371
Song WEdwards DGarside JBainbridge WRosenstiel WMacii E(2012)Area efficient asynchronous SDM routers using 2-stage clos switchesProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493075(1495-1500)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493075
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Index Terms

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors
2. Networks
  1. Network types
    1. Packet-switching networks

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Published In

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

March 2003

292 pages

ISBN:0769518702

Publisher

IEEE Computer Society

United States

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Published: 03 March 2003

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DATE03

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SIGDA

DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Balfour JDally W(2014)Design tradeoffs for tiled CMP on-chip networksACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667187(390-401)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667187
Chen CPark SKrishna TSubramanian SChandrakasan APeh LMacii E(2013)SMARTProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485371(338-343)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485371
Song WEdwards DGarside JBainbridge WRosenstiel WMacii E(2012)Area efficient asynchronous SDM routers using 2-stage clos switchesProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493075(1495-1500)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493075
Stefan RMolnos AAmbrose AGoossens KRosenstiel WMacii E(2012)A TDM NoC supporting QoS, multicast, and fast connection set-upProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493025(1283-1288)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493025
Siéler LDamez LBallet BLandrault ADérutin JLindh L(2011)A generic packet router IP for multi-processors network-on-chipProceedings of the 8th FPGAWorld Conference10.1145/2157871.2157873(1-6)Online publication date: 12-Sep-2011
https://dl.acm.org/doi/10.1145/2157871.2157873
Nitta CFarrens MMacdonald KAkella VMarculescu RKishinevsky MGinosar RChatha K(2011)Inferring packet dependencies to improve trace based simulation of on-chip networksProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999971(153-160)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1999946.1999971
Kao YAlfaraj NYang MChao H(2010)Design of High-Radix Clos Network-on-ChipProceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip10.1109/NOCS.2010.27(181-188)Online publication date: 3-May-2010
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Ludovici DGilabert FMedardoni SGómez CGómez MLópez PGaydadjiev GBertozzi DBenini LDe Micheli GAl-Hashimi BMueller W(2009)Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraintsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874757(562-565)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874757
Gu HXu JZhang WBenini LDe Micheli GAl-Hashimi BMueller W(2009)A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chipProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874625(3-8)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874625
Sekar KLahiri KRaghunathan ADey S(2008)Dynamically configurable bus topologies for high-performance on-chip communicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515843.151585716:10(1413-1426)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.5555/1515843.1515857
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ParIS: a parameterizable interconnect switch for networks-on-chip

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures

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ParIS: a parameterizable interconnect switch for networks-on-chip

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures

Design automation for application-specific on-chip interconnects

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