Article

Challenges in Embedded Memory Design and Test

Authors:

Erik Jan Marinissen,

Betty Prince,

Doris Keitel-Schulz,

Yervant ZorianAuthors Info & Claims

DATE '05: Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Pages 722 - 727

https://doi.org/10.1109/DATE.2005.92

Published: 07 March 2005 Publication History

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Abstract

Both the number of embedded memories, as well as the total embedded memory content inour chips is growing steadily. Time for chip designers, EDA makers, and test engineers to update their knowledge on memories. This Hot Topic paper provides an embedded tutorial on embedded memories, in terms of what is new and coming versus what is old and vanishing, and what are the associated design, test, and repair challenges related to using embedded memories.

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Cited By

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Sumbul HVaidyanathan KZhu QFranchetti FPileggi L(2015)A synthesis methodology for application-specific logic-in-memory designsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744786(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744786
Krishna KSailaja M(2014)Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift RegistersJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5432-130:1(77-85)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1007/s10836-014-5432-1
Chen XLu ZJantsch AChen SChen SGu H(2013)Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data propertyComputers and Electrical Engineering10.1016/j.compeleceng.2012.04.00939:2(596-612)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1016/j.compeleceng.2012.04.009
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Index Terms

Challenges in Embedded Memory Design and Test
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
  2. Document types
    1. Surveys and overviews
2. Hardware

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DATE '05: Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

March 2005

630 pages

ISBN:0769522882

Publisher

IEEE Computer Society

United States

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Published: 07 March 2005

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DATE05: Design, Automation and Test in Europe

March 7 - 11, 2005

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Sumbul HVaidyanathan KZhu QFranchetti FPileggi L(2015)A synthesis methodology for application-specific logic-in-memory designsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744786(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744786
Krishna KSailaja M(2014)Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift RegistersJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5432-130:1(77-85)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1007/s10836-014-5432-1
Chen XLu ZJantsch AChen SChen SGu H(2013)Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data propertyComputers and Electrical Engineering10.1016/j.compeleceng.2012.04.00939:2(596-612)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1016/j.compeleceng.2012.04.009
Liu HPetracca MCarloni LRosenstiel WMacii E(2012)Compositional system-level design exploration with planning of high-level synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492870(641-646)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492870
Ghoshal BKundu SSengupta IChattopadhyay S(2012)Particle swarm optimization based BIST design for memory cores in mesh based network-on-chipProceedings of the 16th international conference on Progress in VLSI Design and Test10.1007/978-3-642-31494-0_39(343-349)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31494-0_39
Goudarzi MIshihara TNoori H(2011)Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologiesTransactions on high-performance embedded architectures and compilers III10.5555/1980776.1980795(275-299)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.5555/1980776.1980795
Sun HLiu CZheng NMin TZhang TAtienza DXie YAyala JStevens K(2011)Design techniques to improve the device write margin for MRAM-based cache memoryProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973030(97-102)Online publication date: 2-May-2011
https://dl.acm.org/doi/10.1145/1973009.1973030
Goudarzi MIshihara TNoori H(2011)Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer TechnologiesProceedings of the 2011 conference on Transactions on High-Performance Embedded Architectures and Compilers III - Volume 659010.1007/978-3-642-19448-1_15(275-299)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1007/978-3-642-19448-1_15
Chen XLu ZJantsch AChen SDe Micheli GAl-Hashimi BMueller WMacii E(2010)Supporting distributed shared memory on multi-core network-on-chips using a dual microcoded controllerProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1870939(39-44)Online publication date: 8-Mar-2010
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Naeem AChen XLu ZJantsch A(2010)Scalability of relaxed consistency models in NoC based multicore architecturesACM SIGARCH Computer Architecture News10.1145/1755235.175523837:5(8-15)Online publication date: 6-Apr-2010
https://dl.acm.org/doi/10.1145/1755235.1755238

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Recommendations

Embedded memory technologies: Present and future

Write-activity-aware nand flash memory management for pcm-based embedded systems

Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems

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