Article

A layout dependent full-chip copper electroplating topography model

Authors:

Jianfeng Luo,

Qing Su,

C. Chiang,

J. KawaAuthors Info & Claims

ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Pages 133 - 140

Published: 31 May 2005 Publication History

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Abstract

In this paper, a layout dependent full-chip electroplating (ECP) topography model is developed based on the additive nature of the physics of the EP process. Two layout attributes: layout density, and feature perimeter sum are used to compute the post-ECP topography. Under a unified mechanism, two output variables representing the final topography: the array height and the step height are modeled simultaneously. Using the proposed model long-range effects of the ECP process can be incorporated easily as well. The simulation results of our model were verified with test structure experimental data published in the literature and are presented in this paper. The results show that the errors are less than 5%. This model is not limited to the regular test structures; it can also be used for any practical design. The results of such partial application are shown here as well. Our proposed ECP model can be used to model systematic variations caused by an ECP process or by a chemical mechanical planarization (CMP) process. The potential applications of this model include: layout design evaluation for catastrophic failure prevention; yield aware design (design for manufacturability), and variation- aware timing analysis.

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Nieuwoudt AKawa JMassoud Y(2010)Crosstalk-induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201083018:3(378-391)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2010830
Shen YZhou QCai YHong X(2010)ECP- and CMP-aware detailed routing algorithm for DFMIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200802018:1(153-157)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2008020
Chen HChou SWang SChang Y(2009)A novel wire-density-driven full-chip routing system for CMP variation controlIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200915628:2(193-206)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009156
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ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

May 2005

1032 pages

ISBN:078039254X

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IEEE Computer Society

United States

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Published: 31 May 2005

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Nieuwoudt AKawa JMassoud Y(2010)Crosstalk-induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201083018:3(378-391)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2010830
Shen YZhou QCai YHong X(2010)ECP- and CMP-aware detailed routing algorithm for DFMIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200802018:1(153-157)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2008020
Chen HChou SWang SChang Y(2009)A novel wire-density-driven full-chip routing system for CMP variation controlIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200915628:2(193-206)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009156
Jia YCai YHong XLubaszewski MRenovell MGupta R(2008)Full-chip routing system for reducing Cu CMP & ECP variationProceedings of the 21st annual symposium on Integrated circuits and system design10.1145/1404371.1404386(10-15)Online publication date: 1-Sep-2008
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Nieuwoudt AKawa JMassoud YNarayanan VYan ZMacii EBhanja S(2008)Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technologyProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366148(151-154)Online publication date: 4-May-2008
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Kawa JChiang CZhou HMacii EYan ZMassoud Y(2007)DFM issues for 65nm and beyondProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228861(318-322)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228861

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Novel full-chip gridless routing considering double-via insertion

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