Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.5555/1131481.1131666guideproceedingsArticle/Chapter ViewAbstractPublication PagesdateConference Proceedingsconference-collections
Article
Free access

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking

Published: 06 March 2006 Publication History

Abstract

Chip overheating has become a critical problem during test of today's complex core-based systems. In this paper, we address the overheating problem in Network-on-Chip (NoC) systems through thermal optimization using variable-rate on-chip clocking. We control the core temperatures during test scheduling by assigning different test clock frequencies to cores. We present two heuristics to achieve thermal optimization and reduced test time. Experimental results for example NoC systems show that the proposed method can guarantee thermal safety and yield better thermal balance, compared to previous methods using power constraints. Test application time is also reduced.

References

[1]
ASICs Test Methodology, IBM Corporation, Essex Junction, VT 05403.
[2]
L. Benini and G. D. Micheli. Networks on chips: a new SoC paradigm. IEEE Computer, vol. 35, pp. 70--78, 2002.
[3]
G. Chen and S. Sapatnekar. Partition-driven standard cell thermal placement. Proc. Int. Symp. on Physical Design, pp. 75--80, 2003.
[4]
R. M. Chou, K. K. Saluja and V. D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. on CAD, vol. 5, pp. 175--185, Jun 1997.
[5]
C. N. Chu and D. F. Wong. A matrix synthesis approach to thermal placement. IEEE Trans. on CAD, vol. 17, pp. 1166--1174, Nov 1998.
[6]
E. Cota, L. Carro and M. Lubaszewski. Reusing an On-Chip Network for the Test of Core-based Systems. ACM Trans. on Design Automation of Electronic Systems, vol. 18, pp. 471--499, 2004.
[7]
W. Hung et al. Thermal-aware IP virtualization and placement for networks-on-chip architecture. Proc. Int. Conf. on Computer Design, pp. 430--437, 2004.
[8]
V. Iyengar and K. Chakrabarty. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Trans. on CAD, vol. 21, pp. 1088--1094, Sep 2002.
[9]
E. Larsson, K. Arvidsson, H. Fujiwara, and Z. Peng. Efficient test solutions for core-based designs. IEEE Trans. on CAD, vol. 23, pp.758--775, May 2004.
[10]
C. Liu, V. Iyengar, J. Shi and E. Cota. Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking. Proc. VLSI Test Symp., pp.349--354, 2005.
[11]
C. Liu, K. Veeraraghavan and V. Iyengar. Thermal-aware test scheduling and hot spot temperature minimization for core-based systems. Proc. Int. Symp. DFT, to appear, 2005.
[12]
E. J. Marinissen, V. Iyengar, and K. Chakrabarty. A set of benchmarks for modular testing of SOCs. Proc. Int. Test Conf., pp. 521--528, 2002.
[13]
M. Nourani and J. Chin. Test scheduling with power-time trade-off and hot-spot avoidance using MILP. Proc. IEE Computer and Digital Techniques, vol. 151, pp. 341--355, Sep 2004.
[14]
P. Rosinger, B. Al-Hashimi and K. Chakrabarty. Rapid generation of thermal-safe test schedules. Proc. Design, Automation and Test in Europe (DATE) Conf., pp.840--845, 2005.
[15]
K. Skadron et al. Temperature-aware microarchitecture. Proc. Int. Symp. on Computer Architecture, pp. 2--13, 2003.
[16]
E. Tafaj et al. Improving thermal-safe test scheduling for core-based system-on-chip using shift frequency scaling. Proc. Int. Symp. DFT, pp. 544--551, 2005.
[17]
B. Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas. Bringing communication networks on-chip: the test and verification implications. IEEE Communications Mag., vol. 41, pp. 74--81, 2003.
[18]
C. Zeferino, M. Kreutz, L. Carro, and A. Susin. A study on communication issues for systems-on-chip. Proc. Symposium on Integrated Circuits and Systems Design, pp. 121--126, 2002.

Cited By

View all
  • (2019)Thermal-aware Test Scheduling Strategy for Network-on-Chip based SystemsACM Journal on Emerging Technologies in Computing Systems10.1145/324105015:1(1-27)Online publication date: 8-Feb-2019

Recommendations

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings
March 2006
1390 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

Qualifiers

  • Article

Acceptance Rates

DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)10
  • Downloads (Last 6 weeks)2
Reflects downloads up to 10 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (2019)Thermal-aware Test Scheduling Strategy for Network-on-Chip based SystemsACM Journal on Emerging Technologies in Computing Systems10.1145/324105015:1(1-27)Online publication date: 8-Feb-2019

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media