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An ADC-BiST scheme using sequential code analysis

Published: 16 April 2007 Publication History

Abstract

This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysis method is an alternative to histogram based analysis techniques to provide test time improvements, especially when the resources are scarce. In addition to the measurement of DNL and INL, non-monotonic behavior can also be detected with the proposed technique. We present two implementation options based on how much on-chip resources are available. The ramp generator has a high linearity over a full-scale range of 1V and the generated ramp signal is capable of testing 13 --- bit ADCs. The circuit implementation of the ramp generator utilizes a feedback configuration to improve the linearity having an area of 0.017mm2 in 0.5μm process.

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F. Azaïs, S. Bernard, Y. Bertrand, X. Michel, and M. Renovell. A low-cost adaptive ramp generator for analog BIST applications. In IEEE VTS, pages 266--271, Apr 2001.
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F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell. A Low-Cost BIST Architecture for Linear Histogram Testting of ADCs. Springer JET, 17(2):139--147, Apr 2001.
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M. Renovell, F. Azaïs., S. Bernard, and Y. Bertrand. Hardware Resource Minimization for a Histogram-based ADC BIST. In IEEE VTS, pages 247--252, Apr 2000.

Cited By

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  • (2010)A robust ADC code hit counting techniqueProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871349(1749-1754)Online publication date: 8-Mar-2010
  • (2009)An on-chip solution for static ADC test and measurementProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531564(81-86)Online publication date: 10-May-2009
  1. An ADC-BiST scheme using sequential code analysis

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    cover image ACM Conferences
    DATE '07: Proceedings of the conference on Design, automation and test in Europe
    April 2007
    1741 pages
    ISBN:9783981080124

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    EDA Consortium

    San Jose, CA, United States

    Publication History

    Published: 16 April 2007

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    DATE07
    Sponsor:
    • EDAA
    • SIGDA
    • The Russian Academy of Sciences
    DATE07: Design, Automation and Test in Europe
    April 16 - 20, 2007
    Nice, France

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    Overall Acceptance Rate 518 of 1,794 submissions, 29%

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    View all
    • (2010)A robust ADC code hit counting techniqueProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871349(1749-1754)Online publication date: 8-Mar-2010
    • (2009)An on-chip solution for static ADC test and measurementProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531564(81-86)Online publication date: 10-May-2009

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