Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1109/ASPDAC.2007.358062guideproceedingsArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
Article
Free access

Runtime leakage power estimation technique for combinational circuits

Published: 23 January 2007 Publication History

Abstract

This paper carefully examines subthreshold leakage during circuit operation (runtime) and develops a novel analysis technique to capture this important effect, which is currently ignored in traditional steady-state leakage calculation approaches. We implement novel dynamic and static estimation methods that provide significant speed improvements over full SPICE simulations and yield estimation errors of approximately 12% on average compared to more than 2times errors in steady-state based subthreshold leakage analysis.

Cited By

View all
  • (2010)Customizing pattern set for test power reduction via improved X-identification and reorderingProceedings of the 16th ACM/IEEE international symposium on Low power electronics and design10.1145/1840845.1840881(177-182)Online publication date: 18-Aug-2010

Recommendations

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings
ASP-DAC '07: Proceedings of the 2007 Asia and South Pacific Design Automation Conference
January 2007
771 pages
ISBN:1424406293

Publisher

IEEE Computer Society

United States

Publication History

Published: 23 January 2007

Author Tags

  1. SPICE simulations
  2. combinational circuits
  3. dynamic estimation methods
  4. error estimation
  5. runtime leakage power estimation technique
  6. static estimation methods
  7. subthreshold leakage analysis

Qualifiers

  • Article

Acceptance Rates

ASP-DAC '07 Paper Acceptance Rate 131 of 408 submissions, 32%;
Overall Acceptance Rate 466 of 1,454 submissions, 32%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)26
  • Downloads (Last 6 weeks)3
Reflects downloads up to 22 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2010)Customizing pattern set for test power reduction via improved X-identification and reorderingProceedings of the 16th ACM/IEEE international symposium on Low power electronics and design10.1145/1840845.1840881(177-182)Online publication date: 18-Aug-2010

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media