An application-centered design flow for self reconfigurable systems implementation
Pages 248 - 253
Abstract
Up to now every proposed methodology for implementing dynamic self reconfigurable systems is architecture-centered. In most cases the system development process is time consuming and requires a very specific technical background. Aim of this work is to provide a fast brain to bit design flow whose goal is to simplify the dynamic reconfigurable system development process by shifting the designer focus from the architecture point of view to the application point of view: designers will not need to possess Dynamic Reconfigurability expertise but just to be skilled with the application domain.
References
[1]
Katherine Compton and Scott Hauck. Reconfigurable computing: a survey of systems and software. ACM Comput. Surv., 34(2):171--210, 2002.
[2]
V. Rana, M. Santambrogio, and D. Sciuto. Dynamic Reconfigurability in Embedded System Design. Circuits and Systems, IEEE International Symposium on, pp. 2734--2737, 2007.
[3]
Xilinx Inc. OPB HWICAP Product Specification. Technical report, Xilinx Inc., March 2004.
[4]
Xilinx Inc. Two Flows of Partial Reconfiguration: Module Based or Difference Based. Technical Report XAPP290, Xilinx Inc., September 2004.
[5]
D. H. Ballard. Generalizing the hough transform to detect arbitrary shapes. pp. 714--725, 1987.
[6]
P. Bellows and B. Hutchings. Jhdl - an hdl for reconfigurable systems. In FCCM '98: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, page 175, Washington, DC, USA, 1998. IEEE Computer Society.
[7]
Joao M. P. Cardoso and Markus Weinhardt. From c programs to the configure-execute model. In DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, page 10576, USA, 2003.
[8]
Altera Corp. Dsp builder 7.2 reference manual. Technical report, Altera Corp., 2007.
[9]
The MathWorks Inc. Simulink 7.0 - using simulink. Technical report, The MathWorks Inc., September 2006.
[10]
The MathWorks Inc. Simulink hdl coder. Technical report, The MathWorks Inc., September 2006.
[11]
The MathWorks Inc. Embedded matlab language user guide. Technical report, The MathWorks Inc., 2007.
[12]
Xilinx Inc. Early Access Partial Reconfiguration Guide. Technical Report, Xilinx Inc., December 2007.
[13]
Xilinx Inc. System generator for dsp 9.2, user guide. Technical report, Xilinx Inc., October 2007.
[14]
W. Luk, N. Shirazi, and P. Cheung. Modelling and optimising run-time reconfigurable systems. In Kenneth L. Pocek and Jeffrey Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pp. 167--176, Los Alamitos, CA, 1996. IEEE Computer Society Press.
[15]
Michael S Moore, Mark Brooks, Greg Willden, and Sandeep Neema. Keys to Success in Model-Based Design. Technical report, DARPA Mobies project, 2004.
[16]
Kyprianos Papademetriou and Apostolos Dollas. A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems. In Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 307--308, 2006
[17]
Ali Ajdari Rad, Karim Faez, and Navid Qaragozlou. Fast Circle Detection Using Gradient Pair Vectors. In DICTA, pp. 879--888, 2003.
[18]
S. Singh, J. Hogg, and D. Mcauley. Expressing dynamic reconfiguration by partial evaluation. In FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on, pp. 188--194, 1996.
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Published: 19 January 2009
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