research-article

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs

Authors:

F. ClermidyAuthors Info & Claims

NANOARCH '10: Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures

Pages 47 - 52

Published: 17 June 2010 Publication History

Get Access

Abstract

This paper presents a set of circuit design approaches to achieve clocked standard logic cell functions with ambipolar double-gate devices such as the Double Gate Carbon Nanotube FET (DG-CNTFET). The cells presented in this work use the infield controllability of the device to reduce transistor count over conventional standard cells by only requiring n+1 transistors (where n is the fan-in), and achieve improved time delay by a factor of 2 for comparable power consumption.

References

[1]

N. Patil, J. Deng, H.-S. Philip Wong, S. Mitra. "Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits". Proc. of DAC, 2007.

Digital Library

Google Scholar

[2]

Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K.-Ha Kim, and C. M. Lieber. "Logic gates and computation from assembled nanowire building blocks", Science, 249:1313--1317, 2001.

Crossref

Google Scholar

[3]

P.-E. Gaillardon, F. Clermidy, I. O'Connor, R. Daviot, "Reconfigurable logic cells for nanoscale -- Comparison between density and functionality enhancement," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 13--16 December 2009, Hammamet, Tunisia.

Google Scholar

[4]

M. H. Ben Jamaa, K. Mohanram and G. De Micheli, "Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis", Design, Automation and Test in Europe (DATE). March 2009.

Digital Library

Google Scholar

[5]

I. O'Connor et al., "CNTFET Modeling and Reconfigurable Logic-Circuit Design", IEEE Transactions on ciruits and Systems-I: Regular Papers, vol. 54, no. 11, pp. 2365--2379, November 2007.

Crossref

Google Scholar

[6]

Y.-M. Lin et al. "Novel Carbon Nanotube FET Design with Tunable Polarity", Proc. IEDM, pp. 687--690, 2004

Google Scholar

[7]

A. Javey et al. "Self-Aligned Ballistic Molecular Transistors and Electrically Parallel Nanotube Arrays", Nano Letters, vol. 4, no. 7, pp. 1319--1322, 2004.

Crossref

Google Scholar

[8]

L. Ding, A. Tselev, J. Wang, D. Yuan, H. Chu, T. P. McNicholas, Y. Li, J. Liu. "Selective Growth of Well-Aligned Semiconducting Single-Walled Carbon Nanotubes", Nano Letters, vol. 9, no. 2, pp. 800, 2009

Crossref

Google Scholar

[9]

J. Appenzeller, J. Knoch, E. Tutuc, M. Reuter, and S. Guha, "Dual-gate nanowire transistors with nickel silicide contacts", IEDM Technical Digest, 555--558 (2006).

Google Scholar

[10]

M. H. Ben Jamaa, D. Atienza, Y. Leblebici, and G. De Micheli, "Programmable Logic Circuits Based on Ambipolar CNFET", Design Automation Conference (DAC), Anaheim, California, USA, 2008.

Digital Library

Google Scholar

[11]

A. Javey, J. Guo, Q. Wang, M. Lundstrom, H. Dai, "Ballistic Carbon Nanotube Transistors". Nature, vol. 424, pp. 654--657, 2003

Crossref

Google Scholar

Cited By

View all

Jabeur KO'Connor INavarro DLe Beux SMoritz C(2012)Low-power design technique with ambipolar double gate devicesProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures10.1145/2765491.2765495(14-21)Online publication date: 4-Jul-2012
https://dl.acm.org/doi/10.1145/2765491.2765495
Jabeur KO'Connor IYakymets NLe Beux SBrunvard EStevens KCavallaro JZhang T(2012)Ambipolar double-gate FETs for the design of compact logic structuresProceedings of the great lakes symposium on VLSI10.1145/2206781.2206785(3-8)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206785
Zukoski AYang XMohanram KStok LDutt NHassoun S(2011)Universal logic modules based on double-gate carbon nanotube transistorsProceedings of the 48th Design Automation Conference10.1145/2024724.2024921(884-889)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024921
Show More Cited By

Index Terms

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs
1. Hardware

Recommendations

Ambipolar double-gate FETs for the design of compact logic structures
GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

We present in this paper a circuit design approach to achieve compact logic circuits with ambipolar double-gate devices, using the in-field controllability of such devices. The approach is demonstrated for complementary static logic design style. We ...
Fine-grain reconfigurable logic cells based on double-gate CNTFETs
GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

This paper presents 2-inputs cells designed to perform reconfigurable operations in nanometric systems exploiting the ambipolar property of double-gate (DG) carbon nanotube (CNT) FETs. Previous work [1] described a dynamic logic cell generating only 14 ...
Low-power design technique with ambipolar double gate devices
NANOARCH '12: Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

Ambipolar FETs with channels composed of carbon nanotubes, graphene or undoped silicon nanowires have a V_ds-dependent I_off, a source of high leakage, as well as a low V_TH, a source of high dynamic power. In this paper, we propose a circuit design ...

Comments

Information & Contributors

Information

Published In

NANOARCH '10: Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures

June 2010

90 pages

ISBN:9781424480180

General Chair:
Shamik Das
MITRE
,
Program Chairs:
Iris Bahar
Brown Univ.
,
Michael Niemier
Univ. of Notre Dame

Publisher

IEEE Press

Publication History

Published: 17 June 2010

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Agence Nationale de la Recherche

Conference

Nanoarch '10

Sponsor:

SIGDA

Nanoarch '10: IEEE/ACM International Symposium on Nanoscale Architectures

June 17 - 18, 2010

California, Anaheim

Acceptance Rates

Overall Acceptance Rate 55 of 87 submissions, 63%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
122
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Jabeur KO'Connor INavarro DLe Beux SMoritz C(2012)Low-power design technique with ambipolar double gate devicesProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures10.1145/2765491.2765495(14-21)Online publication date: 4-Jul-2012
https://dl.acm.org/doi/10.1145/2765491.2765495
Jabeur KO'Connor IYakymets NLe Beux SBrunvard EStevens KCavallaro JZhang T(2012)Ambipolar double-gate FETs for the design of compact logic structuresProceedings of the great lakes symposium on VLSI10.1145/2206781.2206785(3-8)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206785
Zukoski AYang XMohanram KStok LDutt NHassoun S(2011)Universal logic modules based on double-gate carbon nanotube transistorsProceedings of the 48th Design Automation Conference10.1145/2024724.2024921(884-889)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024921
Jabeur KYakymets NO'Connor ILe-Beux SAtienza DXie YAyala JStevens K(2011)Fine-grain reconfigurable logic cells based on double-gate CNTFETsProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973014(19-24)Online publication date: 2-May-2011
https://dl.acm.org/doi/10.1145/1973009.1973014
Jabeur KYakymets NO'Connor ILe Beux S(2011)Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cellsProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941499(162-168)Online publication date: 8-Jun-2011
https://dl.acm.org/doi/10.1109/NANOARCH.2011.5941499

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Ambipolar double-gate FETs for the design of compact logic structures

Fine-grain reconfigurable logic cells based on double-gate CNTFETs

Low-power design technique with ambipolar double gate devices

Comments

Published In

Sponsors

Publisher

Publication History

Check for updates

Author Tags

Qualifiers

Funding Sources

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Ambipolar double-gate FETs for the design of compact logic structures

Fine-grain reconfigurable logic cells based on double-gate CNTFETs

Low-power design technique with ambipolar double gate devices

Comments

Information

Published In

Sponsors

Publisher

Publication History

Check for updates

Author Tags

Qualifiers

Funding Sources

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations