MICRO

This paper presents a hierarchical firmware design method. It allows to structure the design of a microprogrammed (level of a) computer architecture into independently verifiable modules. To specify the behaviour of the system we use the axiomatic ...

The paper is concerned with efficient implementation of evolved modular and structured microprogramming. A microprogrammable architecture is presented that permits designing hierarchical complicated modular microprograms at two distinct levels: the ...

This paper discusses the design and implementation of a debugging/diagnostic subsystem for a bit-slice processor. The subsystem uses serial shadow registers under the control of a single chip microcomputer both to observe and to control processor ...

This paper describes a microcode-evaluation methodology. The supporting test tools were developed by the IBM General Products Division in Tucson, Arizona, to allow effective and comprehensive evaluations of microcode systems. The methodology has been ...

We apply the verification methodology underlying the S*-System[12], [13] to the verification of a hierarchically structured design [16] of an emulation of the instruction-set of a commercially available computer on a commercially available micro-...

A proven method of obtaining high performance for Prolog programs is to first translate them into the instruction set of Warren's Abstract Machine, or W-code [1]. From that point, there are several models of execution available. This paper describes one ...

This paper describes the architecture and the current implementation of the hardware unification unit (HUU). The HUU performs the literal unification operation in Prolog processing. It is designed as a coprocessor to a host system that handles other ...

HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale ...

HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, ...

Current digital logic simulators running on engineering workstations lack capacity and speed. This paper discusses a hardware accelerator for a workstation simulator which addresses these problems. The accelerator runs 100x faster than its software ...

Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. ...

We describe a system which allows high-level microprogramming without requiring programmer knowledge of the target architecture, depending instead on retargetable microcode generation and optimization. In the ideal system the code generation, microcode ...

The aim of this paper is to develop a top-down design automation tool for digital system design such as microprogrammed processors. The package contains a hardware description language to specify the design, a microcode development module to generate an ...

STEP Development Tools (SDT) is a general-purpose microprogram development system. The METASTEP language system is composed of four tools of the SDT needed to write microprograms: a Definition Processor, a Retargetable Assembler, a Retargetable Cross-...

We believe that the intellectual efforts of persons should be protected, but that the needs of society must be protected, too. Substantial interest in this issue, as it pertains to the protection of microcode, has prompted the preparation of this paper ...

Global microcode compaction is an open problem in firmware engineering. Although Fisher's trace scheduling method may produce significant reductions in the execution time of compacted microcode, it has some drawbacks. There have been four methods. Tree, ...

JAM (Just Another Microsequencer) is a flexible - dual role microcode sequencer. It supports high performance N-Way microsequencing operations (traditional 360/370 type branch address generation techniques), along with more traditional (a la AMD 2910) ...

The paper reports on the control store cost minimization using an approach related to the bit reduction method. A methodology is presented for finding the microinstruction format which provides a minimum joint cost of the control store and ...