An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow ...

Null convention logic (NCL) is a good design approach for constructing a low-power and high-speed asynchronous system. However, NCL has a higher transistor count with a dual-rail structure, especially for large-scale circuits. To save NCL dual-...

An asynchronous circuit uses components to communicate with a handshake protocol. The handshake protocol defines communication agreement and data encoding; it provides a mechanism to ensure data flow between two registers (or latches) without conflict. A ...

Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a satisfactory performance and power tradeoff. We design FPGA circuits and ...