research-article

An integer programming placement approach to FPGA clock power reduction

Authors:

Alireza Rakhshanfar,

Jason H. AndersonAuthors Info & Claims

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

Pages 831 - 836

Published: 25 January 2011 Publication History

Abstract

Clock signals are responsible for a significant portion of dynamic power in FPGAs owing to their high toggle frequency and capacitance. Clock signals are distributed to loads through a programmable routing tree network, designed to provide low delay and low skew. The placement step of the FPGA CAD flow plays a key role in influencing clock power, as clock tree branches are connected based solely on the placement of the clock loads. In this paper, we present a placement-based approach to clock power reduction based on an integer linear programming (ILP) formulation. Our technique is intended to be used as an optimization post-pass executed after traditional placement, and it offers fine-grained control of the amount by which clock power is optimized versus other placement criteria. Results show that the proposed technique reduces clock network capacitance by over 50% with minimal deleterious impact on post-routed wirelength and circuit speed.

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Cited By

Ebeling CHow DLewis DSchmit HChen DGreene J(2016)Stratix™ 10 High Performance Routable Clock NetworksProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847279(64-73)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847279

Index Terms

An integer programming placement approach to FPGA clock power reduction

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Published In

cover image ACM Conferences

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

January 2011

841 pages

ISBN:9781424475162

Sponsors

IEEE
IPSJ
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IEICE

Publisher

IEEE Press

Publication History

Published: 25 January 2011

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ASPDAC '11

Sponsor:

SIGDA
IEICE ESS

ASPDAC '11: 16th Asia and South Pacific Design Automation Conference

January 25 - 28, 2011

Yokohama, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Ebeling CHow DLewis DSchmit HChen DGreene J(2016)Stratix™ 10 High Performance Routable Clock NetworksProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847279(64-73)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847279

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