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Cited By

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Touati S(2018)Register saturation in instruction level parallelismInternational Journal of Parallel Programming10.1007/s10766-005-6466-x33:4(393-449)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s10766-005-6466-x
Touati S(2007)On Periodic Register Need in Software PipeliningIEEE Transactions on Computers10.1109/TC.2007.7075256:11(1493-1504)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1109/TC.2007.70752
Touati S(2005)On the Optimality of Register SaturationElectronic Notes in Theoretical Computer Science (ENTCS)10.1016/j.entcs.2005.01.033132:1(131-148)Online publication date: 1-May-2005
https://dl.acm.org/doi/10.1016/j.entcs.2005.01.033
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Index Terms

Allocating registers in multiple instruction-issuing processors

Recommendations

Multiple, out-of-order, instruction issuing system for superscalar processors
Allocating architected registers through differential encoding

Micro-architecture designers are very cautious about expanding the number of architected and exposed registers in the instruction set because increasing the register field adds to the code size, raises the I-cache and memory pressure, and may complicate ...
An evaluation of speculative instruction execution on simultaneous multithreaded processors

Modern superscalar processors rely heavily on speculative execution for performance. For example, our measurements show that on a 6-issue superscalar, 93% of committed instructions for SPECINT95 are speculative. Without speculation, processor resources ...

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Published In

PACT '95: Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques

June 1995

324 pages

ISBN:0897917456

Chairmen:
Lubomir Bic
Univ. of California, Irvine
,
Paraskevas Evripidou
Univ. of Cyprus
,
Wim Böhm
Colorado State Univ.
,
Jean-Luc Gaudiot
Univ. of Southern California

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IFIP Working Group on Algol

United Kingdom

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Published: 27 June 1995

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PACT95

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SIGARCH

PACT95: International Conference on Parallel Architectures and Compilation Techniques

June 27 - 29, 1995

Limassol, Cyprus

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Overall Acceptance Rate 121 of 471 submissions, 26%

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Touati S(2018)Register saturation in instruction level parallelismInternational Journal of Parallel Programming10.1007/s10766-005-6466-x33:4(393-449)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s10766-005-6466-x
Touati S(2007)On Periodic Register Need in Software PipeliningIEEE Transactions on Computers10.1109/TC.2007.7075256:11(1493-1504)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1109/TC.2007.70752
Touati S(2005)On the Optimality of Register SaturationElectronic Notes in Theoretical Computer Science (ENTCS)10.1016/j.entcs.2005.01.033132:1(131-148)Online publication date: 1-May-2005
https://dl.acm.org/doi/10.1016/j.entcs.2005.01.033
Touati SMadsen JHenkel JHu X(2001)Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systemsProceedings of the ninth international symposium on Hardware/software codesign10.1145/371636.371709(159-164)Online publication date: 25-Apr-2001
https://dl.acm.org/doi/10.1145/371636.371709

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Index Terms

Recommendations

Multiple, out-of-order, instruction issuing system for superscalar processors

Allocating architected registers through differential encoding

An evaluation of speculative instruction execution on simultaneous multithreaded processors

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