research-article

Revisiting hardware-assisted page walks for virtualized systems

Authors:

Jaehyuk HuhAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 40, Issue 3

Pages 476 - 487

https://doi.org/10.1145/2366231.2337214

Published: 09 June 2012 Publication History

Abstract

Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current two-dimensional (2D) page walkers have been designed under the assumption that the usage patterns of guest and nested page tables are similar. In this paper, we revisit the architectural supports for nested page table walks to incorporate the unique characteristics of memory management by hypervisors. Unlike page tables in native systems, nested page table sizes do not impose significant overheads on the overall memory usage. Based on this observation, we propose to use flat nested page tables to reduce unnecessary memory references for nested walks.

A competing mechanism to HW 2D page walkers is shadow paging, which duplicates guest page tables but provides direct translations from guest virtual to system physical addresses. However, shadow paging has been suffering from the overheads of synchronization between guest and shadow page tables. The second mechanism we propose is a speculative shadow paging mechanism, called speculative inverted shadow paging, which is backed by non-speculative flat nested page tables. The speculative mechanism provides a direct translation with a single memory reference for common cases, and eliminates the page table synchronization overheads. We evaluate the proposed schemes with the real Xen hypervisor running on a full system simulator. The flat page tables improve a state-of-the-art 2D page walker with a page walk cache and nested TLB by 7%. The speculative shadow paging improves the same 2D page walker by 14%.

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Cited By

Ainsworth SJones TWang ZWrigstad T(2021)Compendia: reducing virtual-memory costs via selective densificationProceedings of the 2021 ACM SIGPLAN International Symposium on Memory Management10.1145/3459898.3463902(52-65)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3459898.3463902
Song WDelimitrou CShen ZRenesse RWeatherspoon HBenmohamed LVaulx FMahmoudi C(2021)CacheInspectorACM Transactions on Architecture and Code Optimization10.1145/345737318:3(1-25)Online publication date: 8-Jun-2021
https://dl.acm.org/doi/10.1145/3457373
Szefer J(2018)Principles of Secure Processor Architecture DesignSynthesis Lectures on Computer Architecture10.2200/S00864ED1V01Y201807CAC04513:3(1-173)Online publication date: 18-Oct-2018
https://doi.org/10.2200/S00864ED1V01Y201807CAC045
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Index Terms

Revisiting hardware-assisted page walks for virtualized systems
1. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Virtual memory

Index terms have been assigned to the content through auto-classification.

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 40, Issue 3

ISCA '12

June 2012

559 pages

ISSN:0163-5964

DOI:10.1145/2366231

Issue’s Table of Contents

ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
June 2012
584 pages
ISBN:9781450316422
General Chair:
Shih-Lien Lu
Intel
,
Program Chair:
Josep Torrellas
University of Illinois

Copyright © 2012 ACM.

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Association for Computing Machinery

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Published: 09 June 2012

Published in SIGARCH Volume 40, Issue 3

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Cited By

Ainsworth SJones TWang ZWrigstad T(2021)Compendia: reducing virtual-memory costs via selective densificationProceedings of the 2021 ACM SIGPLAN International Symposium on Memory Management10.1145/3459898.3463902(52-65)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3459898.3463902
Song WDelimitrou CShen ZRenesse RWeatherspoon HBenmohamed LVaulx FMahmoudi C(2021)CacheInspectorACM Transactions on Architecture and Code Optimization10.1145/345737318:3(1-25)Online publication date: 8-Jun-2021
https://dl.acm.org/doi/10.1145/3457373
Szefer J(2018)Principles of Secure Processor Architecture DesignSynthesis Lectures on Computer Architecture10.2200/S00864ED1V01Y201807CAC04513:3(1-173)Online publication date: 18-Oct-2018
https://doi.org/10.2200/S00864ED1V01Y201807CAC045
Ausavarungnirun RLandgraf JMiller VGhose SGandhi JRossbach CMutlu OHunter HMoreno JEmer JSanchez D(2017)MosaicProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123975(136-150)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123975
Wang XLuo THu JWang ZLuo Y(2016)Evaluating the impacts of hugepage on virtual machines评估大页对内存虚拟化的影响Science China Information Sciences10.1007/s11432-015-0764-760:1Online publication date: 29-Nov-2016
https://doi.org/10.1007/s11432-015-0764-7
Zhang JJia WChai SLiu PKim JXu TTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Direct Memory Translation for Virtualized CloudsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640358(287-304)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640358
Zhao KXue KWang ZSchatzberg DYang LManousis AWeiner JVan Riel RSharma BTang CSkarlatos DSolihin YHeinrich M(2023)Contiguitas: The Pursuit of Physical Memory Contiguity in DatacentersProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589079(1-15)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589079
Stojkovic JSkarlatos DKokolis AXu TTorrellas JFalsafi BFerdman MLu SWenisch T(2022)Parallel virtualized memory translation with nested elastic cuckoo page tablesProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507720(84-97)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507720
Bitchebe SMvondo DRéveillère Lde Palma NTchana ATitzer BXu HZhang I(2021)Extending Intel PML for hardware-assisted working set size estimation of VMsProceedings of the 17th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments10.1145/3453933.3454018(111-124)Online publication date: 7-Apr-2021
https://dl.acm.org/doi/10.1145/3453933.3454018
Teabe BYuhala PTchana AHermenier FHagimont DMuller GTitzer BXu HZhang I(2021)(No)Compromis: paging virtualization is not a fatalityProceedings of the 17th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments10.1145/3453933.3454013(43-56)Online publication date: 7-Apr-2021
https://dl.acm.org/doi/10.1145/3453933.3454013
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