research-article

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems

Authors:

Yaojun Zhang Li,

Yiran ChenAuthors Info & Claims

DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 380 - 385

Published: 18 March 2013 Publication History

Abstract

Program disturb, read disturb and retention time limit are three major reasons accounting for the bit errors in NAND flash memory. The adoption of multi-level cell (MLC) technology and technology scaling further aggravates this reliability issue by narrowing threshold voltage noise margins and introducing larger device variations. Besides implementing error correction code (ECC) in NAND flash modules, RAID-5 are often deployed at system level to protect the data integrity of NAND flash storage systems (NFSS), however, with significant performance degradation. In this work, we propose a technique called "DA-RAID-5" to improve the performance of the enterprise NFSS under RAID-5 protection without harming its reliability (here DA stands for "disturb aware"). Three schemes, namely, unbound-disturb limiting (UDL), PE-aware RAID-5 and Hybrid Caching(HC) are proposed to protect the NFSS at the different stages of its lifetime. The experimental results show that compared to the best prior work, DA-RAID-5 can improve the NFSS response time by 9.7% on average.

References

[1]

T. Jung, Y. Choi, K. Suh, B. Suh, J. Kim, Y. Lim, Y. Koh, J. Park, K. Lee, J. Park et al., "A 3.3 v 128 mb multi-level nand flash memory for mass storage applications," in 42nd ISSCC. IEEE, 1996, pp. 32--33.

[2]

A. Brand, K. Wu, S. Pan, and D. Chin, "Novel read disturb failure mechanism induced by flash cycling," in 31st IRPS, 1993, pp. 127--132.

[3]

T. Wang, W. Tsai, S. Gu, C. Chan, C. Yeh, N. Zous, T. Lu, S. Pan, and C. Lu, "Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells," in IEDM. IEEE, 2003, pp. 7--4.

[4]

C. Xue, Y. Zhang, Y. Chen, G. Sun, J. Yang, and H. Li, "Emerging nonvolatile memories: Opportunities and challenges," in 7th CODES+ISSS. ACM, 2011, pp. 325--334.

Digital Library

[5]

Y. Lee, S. Jung, and Y. Song, "Fra: a flash-aware redundancy array of flash storage devices," in 7th CODES+ISSS, 2009, pp. 163--172.

Digital Library

[6]

S. Lee, B. Lee, K. Koh, and H. Bahn, "A lifespan-aware reliability scheme for raid-based flash storage," in SAC, 2011, pp. 374--379.

Digital Library

[7]

S. Im and D. Shin, "Flash-aware raid techniques for dependable and high-performance flash memory ssd," IEEE Transactions on Computers, vol. 60, no. 1, pp. 80--92, 2011.

Digital Library

[8]

Y. Pan, G. Dong, and T. Zhang, "Exploiting memory device wear-out dynamics to improve nand flash memory system performance," in 9th FAST, 2011.

Digital Library

[9]

L. Grupp, A. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P. Siegel, and J. Wolf, "Characterizing flash memory: anomalies, observations, and applications," in 42nd MICRO, 2009, pp. 24--33.

Digital Library

[10]

N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. Nevill, "Bit error rate in nand flash memories," in 46th IRPS. IEEE, 2008, pp. 9--19.

[11]

M. Kang, K. Park, Y. Song, Y. Lim, K. Suh, and H. Shin, "Improving read disturb characteristics by using double common source line and dummy switch architecture in multi level cell nand flash memory with low power consumption," Japanese JAP, vol. 50, no. 4, 2011.

[12]

J. Lee, J. Choi, D. Park, and K. Kim, "Data retention characteristics of sub-100 nm nand flash memory cells," EDL, vol. 24, no. 12, pp. 748--750, 2003.

[13]

L. Shi, C. Xue, and X. Zhou, "Cooperating write buffer cache and virtual memory management for flash memory based systems," in RTAS. IEEE, 2011, pp. 147--156.

Digital Library

[14]

L. Shi, C. Xue, J. Hu, W. Tseng, X. Zhou, and E. Sha, "Write activity reduction on flash main memory via smart victim cache," in 20th GLSVLSI. ACM, 2010, pp. 91--94.

Digital Library

[15]

D. Liu, T. Wang, Y. Wang, Z. Qin, and Z. Shao, "Pcm-ftl: A write-activity-aware nand flash memory management scheme for pcm-based embedded systems," in 32nd RTSS, 2011, pp. 357--366.

Digital Library

[16]

"Oltp application i/o and search engine i/o," http://traces.cs.umass.edu/index.php/storage/storage.

[17]

"A simulator for various ftl scheme," http://csl.cse.psu.edu/?q=node/322.

Cited By

Pan CHo CChang YKuo TChang YYang MHaddad HWainwright RChbeir R(2018)Boosting the performance with a data-backup-free programming scheme for TLC-based SSDsProceedings of the 33rd Annual ACM Symposium on Applied Computing10.1145/3167132.3167171(351-358)Online publication date: 9-Apr-2018
https://dl.acm.org/doi/10.1145/3167132.3167171
Guo JWang DShao ZChen Y(2017)Data-Pattern-Aware Error Prevention Technique to Improve System ReliabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264205525:4(1433-1443)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2642055
Guo JWen WHu JWang DLi HChen Y(2015)FlexLevelProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744843(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744843

Index Terms

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems
1. Hardware

Recommendations

WeLe-RAID: a SSD-based RAID for system endurance and performance
NPC'11: Proceedings of the 8th IFIP international conference on Network and parallel computing

Due to the limited erasure/program cycles of flash memory, flashbased SSDs need to prolong their life time using wear-leveling mechanism to meet their advertised capacity all the time. However, there is no wear-leveling mechanism among SSDs in RAID ...
i-RAID: a novel redundant storage architecture for improving reliability, performance, and life-span of solid-state disk systems
SAC '16: Proceedings of the 31st Annual ACM Symposium on Applied Computing

Solid State Disks (SSDs) are becoming increasingly popular in enterprise applications where high performance and high reliability are paramount. Although SSDs have very low read access time, their write performance is often less ideal. In addition, SSDs ...
A lifespan-aware reliability scheme for RAID-based flash storage
SAC '11: Proceedings of the 2011 ACM Symposium on Applied Computing

Due to the ever-growing capacity of flash memory along with its good properties such as low-power consumption and high performance, flash-based SSDs (solid state disks) are anticipated to be used in the storage of high-end server systems. However, the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe

March 2013

1944 pages

ISBN:9781450321532

General Chair:
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 18 March 2013

Check for updates

Qualifiers

Research-article

Conference

DATE 13

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE 13: Design, Automation and Test in Europe

March 18 - 22, 2013

Grenoble, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
191
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)1

Reflects downloads up to 13 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Pan CHo CChang YKuo TChang YYang MHaddad HWainwright RChbeir R(2018)Boosting the performance with a data-backup-free programming scheme for TLC-based SSDsProceedings of the 33rd Annual ACM Symposium on Applied Computing10.1145/3167132.3167171(351-358)Online publication date: 9-Apr-2018
https://dl.acm.org/doi/10.1145/3167132.3167171
Guo JWang DShao ZChen Y(2017)Data-Pattern-Aware Error Prevention Technique to Improve System ReliabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264205525:4(1433-1443)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2642055
Guo JWen WHu JWang DLi HChen Y(2015)FlexLevelProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744843(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744843

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents