Article

Acceldroid: Co-designed acceleration of Android bytecode

Authors:

Marcelo Cintra, and

Youfeng WuAuthors Info & Claims

CGO '13: Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

February 2013

Pages 1 - 10

https://doi.org/10.1109/CGO.2013.6494980

Published: 23 February 2013 Publication History

Abstract

A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations. It leverages co-designed HW features and dynamic binary translation (DBT) SW to morph existing binary programs to scale performance and save power. On such systems, the portable bytecode of modern dynamic languages (e.g. Java, JavaScript, etc.) is first translated into the code in the architecture ISA by the just-in-time (JIT) compilation in the bytecode virtual machine, and then into the code in the internal implementation ISA by the DBT. This not only incurs the translation overheads twice, but also brings significant emulation inefficiency as the DBT does not have the high level bytecode information. In this paper, we present AccelDroid, which accelerates the Android Dalvik bytecode execution on the HW/SW co-designed processor through direct bytecode translation in the DBT. Our experiments on a HW/SW co-designed Transmeta Efficeon machine show that AccelDroid can improve performance by 78% and save energy by 40% for the CaffeineMark 3.0 benchmark suite.

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Cited By

Kumar RMartínez AGonzález A(2016)Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned EnvironmentACM Transactions on Computer Systems10.1145/280769433:4(1-33)Online publication date: 4-Jan-2016
https://dl.acm.org/doi/10.1145/2807694
Alam FPanda PTripathi NSharma NNarayan SFettweis GNebel W(2014)Energy optimization in android applications through wakelock placementProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616714(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616714
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel D(2014)Speculative hardware/software co-designed floating-point multiply-add fusionACM SIGARCH Computer Architecture News10.1145/2654822.254197842:1(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2654822.2541978
Show More Cited By

Index Terms

Acceldroid: Co-designed acceleration of Android bytecode
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
    2. General programming languages
      1. Language types

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cover image ACM Conferences

CGO '13: Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

February 2013

366 pages

ISBN:9781467355247

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IEEE Computer Society

United States

Publication History

Published: 23 February 2013

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Cited By

Kumar RMartínez AGonzález A(2016)Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned EnvironmentACM Transactions on Computer Systems10.1145/280769433:4(1-33)Online publication date: 4-Jan-2016
https://dl.acm.org/doi/10.1145/2807694
Alam FPanda PTripathi NSharma NNarayan SFettweis GNebel W(2014)Energy optimization in android applications through wakelock placementProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616714(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616714
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel D(2014)Speculative hardware/software co-designed floating-point multiply-add fusionACM SIGARCH Computer Architecture News10.1145/2654822.254197842:1(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2654822.2541978
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel D(2014)Speculative hardware/software co-designed floating-point multiply-add fusionACM SIGPLAN Notices10.1145/2644865.254197849:4(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2644865.2541978
Kumar RMartínez AGonzález A(2014)Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned EnvironmentACM Transactions on Architecture and Code Optimization10.1145/262968111:3(1-23)Online publication date: 31-Jul-2014
https://dl.acm.org/doi/10.1145/2629681
Branković AStavrou KGibert EGonzález ATrancoso PFranklin DMcKee S(2014)Accurate off-line phase classification for HW/SW co-designed processorsProceedings of the 11th ACM Conference on Computing Frontiers10.1145/2597917.2597937(1-10)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2597917.2597937
Branković AStavrou KGibert EGonzález A(2014)Warm-Up Simulation Methodology for HW/SW Co-Designed ProcessorsProceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization10.1145/2581122.2544142(284-294)Online publication date: 15-Feb-2014
https://dl.acm.org/doi/10.1145/2581122.2544142
Branković AStavrou KGibert EGonzález A(2014)Warm-Up Simulation Methodology for HW/SW Co-Designed ProcessorsProceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization10.1145/2544137.2544142(284-294)Online publication date: 15-Feb-2014
https://dl.acm.org/doi/10.1145/2544137.2544142
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel DBalasubramonian RDavis AAdve S(2014)Speculative hardware/software co-designed floating-point multiply-add fusionProceedings of the 19th international conference on Architectural support for programming languages and operating systems10.1145/2541940.2541978(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2541940.2541978

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