research-article

ForTER: a forward error correction scheme for timing error resilience

Authors:

Qiang XuAuthors Info & Claims

ICCAD '13: Proceedings of the International Conference on Computer-Aided Design

Pages 55 - 60

Published: 18 November 2013 Publication History

Abstract

With technology scaling, integrated circuits suffer from increasingly severe static and dynamic variations, which often manifest themselves as infrequent timing errors on circuit speed paths, if a large timing guard-band is not reserved. This paper presents a new forward timing error correction scheme, namely ForTER, which predicts whether the occurrence of timing errors would propagate to the next level of sequential elements and corrects them without necessarily borrowing timing slack. The proposed technique can be combined with other timing error resilient circuit design techniques to further improve circuit performance, as demonstrated in our experimental results with various benchmark circuits.

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Cited By

Zhu TMeng JXiang XYan X(2017)Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT ProcessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.265248225:5(1681-1693)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TVLSI.2017.2652482
Chang IPark SChoi J(2017)Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error CancelationCircuits, Systems, and Signal Processing10.1007/s00034-017-0534-536:11(4309-4325)Online publication date: 1-Nov-2017
https://dl.acm.org/doi/10.1007/s00034-017-0534-5

Index Terms

ForTER: a forward error correction scheme for timing error resilience

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Information

Published In

cover image ACM Conferences

ICCAD '13: Proceedings of the International Conference on Computer-Aided Design

November 2013

871 pages

ISBN:9781479910694

General Chair:
Jörg Henkel
Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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IEEE Press

Publication History

Published: 18 November 2013

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Research-article

Conference

ICCAD'13

Sponsor:

SIGDA

ICCAD'13: The International Conference on Computer-Aided Design

November 18 - 21, 2013

California, San Jose

Acceptance Rates

ICCAD '13 Paper Acceptance Rate 92 of 354 submissions, 26%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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ICCAD '24

Sponsor:
sigda

IEEE/ACM International Conference on Computer-Aided Design

October 27 - 31, 2024

New York , NY , USA

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Cited By

Zhu TMeng JXiang XYan X(2017)Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT ProcessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.265248225:5(1681-1693)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TVLSI.2017.2652482
Chang IPark SChoi J(2017)Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error CancelationCircuits, Systems, and Signal Processing10.1007/s00034-017-0534-536:11(4309-4325)Online publication date: 1-Nov-2017
https://dl.acm.org/doi/10.1007/s00034-017-0534-5

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