Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees
Authors: 
Heechun Park, Taewhan KimAuthors Info & Claims
Heechun Park, Taewhan KimAuthors Info & ClaimsAbstract
Recently, to cope with clock TSV (Through-Silicon-Via) reliability problem efficiently, a new circuit structure called TSV Fault-tolerant Unit (TFU) and the allocation method of TFUs have been proposed. However, the existing design methods partially or never addressed following key issues: (1) the feasibility of TSV pairing for TFU allocation, (2) maximizing TSV pairing, (3) supporting the slew and delay control capability in TFU for the cases of pre-bond testing as well as post-bond stage, and (4) minimizing the impact of TFU insertion on the clock skew of the whole 3D clock tree. In this work, we propose a full solution to the problem of designing and synthesizing TSV fault-tolerant clock tree from a 3D clock tree, which effectively addresses above key issues.
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Index Terms
- Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees
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Published: 18 November 2013
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ICCAD'13: The International Conference on Computer-Aided Design
November 18 - 21, 2013
California, San Jose
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ICCAD '13 Paper Acceptance Rate 92 of 354 submissions, 26%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%
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