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The filter cache: an energy efficient memory structure

Authors:

Johnson Kin,

Munish Gupta,

William H. Mangione-SmithAuthors Info & Claims

MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

Pages 184 - 193

Published: 01 December 1997 Publication History

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Abstract

Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many applications, such as portable devices, low power is more important than performance. We propose to trade performance for power consumption by filtering cache references through an unusually small L1 cache. An L2 cache, which is similar in size and structure to a typical L1 cache, is positioned behind the filter cache and serves to reduce the performance loss. Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency. For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over conventional design.

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The filter cache: an energy efficient memory structure

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Published In

MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

December 1997

369 pages

ISBN:0818679778

Chairmen:
Mark Smotherman
Clemson Univ., Clemson, SC
,
Tom Conte
North Carolina State Univ., Raleigh

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 1997

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MICRO97

Sponsor:

SIGMICRO
IEEE-CS\TCMM

MICRO97: 30th Annual International Symposium on Microarchitecture

December 1 - 3, 1997

North Carolina, Research Triangle Park, USA

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MICRO 30 Paper Acceptance Rate 35 of 103 submissions, 34%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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https://dl.acm.org/doi/10.1109/ISCA45697.2020.00022
Stokes MBaird RJin ZWhalley DOnder S(2018)Decoupling address generation from loads and stores to improve data access energy efficiencyACM SIGPLAN Notices10.1145/3299710.321134053:6(65-75)Online publication date: 19-Jun-2018
https://dl.acm.org/doi/10.1145/3299710.3211340
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A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches

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