research-article

Exploiting DRAM restore time variations in deep sub-micron scaling

Authors:

Bruce R. Childers,

Jun YangAuthors Info & Claims

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

Pages 477 - 482

Published: 09 March 2015 Publication History

Abstract

Recent studies reveal that one of the major challenges in scaling DRAM in deep sub-micron regime is its significant variations on cell restore time, which affects timing constraints such as write recovery time tWR. Adopting traditional approaches results in either low yield rate or large performance degradation. In this paper, we propose schemes to expose the variations to the architectural level. By constructing memory chunks with different accessing speeds and, in particular, exploiting the performance benefits of fast chunks, a variation-aware memory controller can effectively compensate the performance loss due to relaxed timing constraints. Our experimental results show that, comparing to traditional designs such as row sparing and ECC, the proposed schemes help to improve system performance by up to 10.3% and 12.9%, respectively, for 20nm and 14nm tech nodes on a 4-core multiprocessor system.

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Cited By

Hassan HPatel MKim JYaglikci AVijaykumar NGhiasi NGhose SMutlu OManne SHunter HAltman E(2019)CROWProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322231(129-142)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322231
Zhang XWang RZhang YYang JShibuya T(2019)Boosting chipkill capability under retention-error induced reliability emergencyProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287639(400-405)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287639
Zhao LZhang YYang JParameswaran S(2017)AEPProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199845(1047-1053)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199845
Show More Cited By

Index Terms

Exploiting DRAM restore time variations in deep sub-micron scaling
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Information

Published In

cover image ACM Conferences

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

March 2015

1827 pages

ISBN:9783981537048

General Chair:
Wolfgang Nebel
OFFIS & University of Oldenburg, DE
,
Program Chair:
David Atienza
EPFL, CH

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
Russian Acadamy of Sciences: Russian Acadamy of Sciences
IEEE Council on Electronic Design Automation (CEDA)

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 09 March 2015

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DATE '15: Design, Automation and Test in Europe

March 9 - 13, 2015

Grenoble, France

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DATE '15 Paper Acceptance Rate 206 of 915 submissions, 23%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Hassan HPatel MKim JYaglikci AVijaykumar NGhiasi NGhose SMutlu OManne SHunter HAltman E(2019)CROWProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322231(129-142)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322231
Zhang XWang RZhang YYang JShibuya T(2019)Boosting chipkill capability under retention-error induced reliability emergencyProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287639(400-405)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287639
Zhao LZhang YYang JParameswaran S(2017)AEPProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199845(1047-1053)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199845
Zhao LZhang YYang JParameswaran S(2017)AEPProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199802(765-771)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199802
Mathew DZulian ÉJung MKraft KWeis CJacob BWehn NJacob B(2017)Using run-time reverse-engineering to optimize DRAM refreshProceedings of the International Symposium on Memory Systems10.1145/3132402.3132419(115-124)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132419
Zhang XZhang YChilders BYang J(2017)On the Restore Time Variations of Future DRAM MemoryACM Transactions on Design Automation of Electronic Systems10.1145/296760922:2(1-24)Online publication date: 9-Feb-2017
https://dl.acm.org/doi/10.1145/2967609
Zhang XZhang YChilders BYang JJacob B(2016)AWARDProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989127(322-324)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.1145/2989081.2989127
Chen RWang YHu JLiu DShao ZGuan Y(2016)Image-Content-Aware I/O Optimization for Mobile VirtualizationACM Transactions on Embedded Computing Systems10.1145/295005916:1(1-24)Online publication date: 13-Oct-2016
https://dl.acm.org/doi/10.1145/2950059
Childers BYang JZhang Y(2015)Achieving Yield, Density and Performance Effective DRAM at Extreme Technology SizesProceedings of the 2015 International Symposium on Memory Systems10.1145/2818950.2818963(78-84)Online publication date: 5-Oct-2015
https://dl.acm.org/doi/10.1145/2818950.2818963

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