Potential applications based on NVM emerging technologies
Authors: 
Sophiane Senni, Raphael Martins Brum, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatie, Bruno MussardAuthors Info & Claims
Sophiane Senni, Raphael Martins Brum, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatie, Bruno MussardAuthors Info & ClaimsPages 1012 - 1017
Abstract
Energy efficiency is a critical figure of merit for battery-powered applications. Today's embedded systems suffer from significant increase of power consumption essentially due to a high leakage current in advanced technology node. A significant portion of the total power consumption is spent into memory systems because of an increasing trend of embedded volatile memory area among the building components in System-on-Chips (SoCs). That is why new Non-Volatile Memory (NVM) technologies are considered as a potential solution to solve the energy efficiency issue. Among these NVM technologies, Magnetic RAM (MRAM) is a promising candidate to replace current memories since it combines non-volatility, high scalability, high density, low latency and low leakage. This paper explores use of MRAM into a memory hierarchy (from cache memory to register) of a processor-based system analyzing both performance and energy consumption.
References
[1]
B. N. Engel et al., "A 4-Mb Toggle MRAM Based on a Novel Bit and Switching Method," in IEEE Transactions on Magnetics, vol. 41, no. 1, January 2005.
[2]
A. V. Khvalkovskiy et al., << Basic principles of STT-MRAM cell operation in memory arrays," in Journal of Physics D: Applied Physics, vol. 46, no. 7, 2013.
[3]
I. L. Prejbeanu et al., "Thermally assisted MRAM," in Journal of Physics: Condensed Matter, vol. 19, no. 16, 2007.
[4]
N. Binkert, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, D. A. Wood, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, and T. Krishna, "The gem5 simulator," ACM SIGARCH Computer Architecture News, vol. 39, no. 2, pp. 1--7, Aug. 2011.
[5]
X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, "NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 7, pp. 994--1007, Jul. 2012
[6]
J. Wang, X. Dong and Y. Xie, "OAP: an obstruction-aware cache management policy for STT-RAM last-level caches," in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 847--852, March 2013.
[7]
R. Bishnoi, M. Ebrahimi, F. Oboril and M. Tahoori, "Architectural Aspects in Design and Analysis of SOT-Based Memories," in the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 700--707, January 2014.
[8]
E. Arima et al., "Fine-Grain Power-Gating on STT-MRAM Peripheral Circuits with Locality-aware Access Control," in The Memory Forum (in conjounction with the 41st International Symposium on Computer Architecture), June 2014, unpublished.
[9]
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations," in Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 24--36, June 1995.
[10]
T. Na, K. Ryu, J. Kim, S. H. Kang, and S. Jung., "A Comparative Study of STT-MTJ based Non-Volatile Flip-Flops," in Circuits and Systems (ISCAS), IEEE International Symposium on, pages 109--112, May 2013.
[11]
D. Suzuki, M. Natsui, A. Mochizuki et al., "Design and fabrication of a perpendicular MTJ based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure," Journal of Applied Physics, 115, 17B742 (2014).
[12]
W. C. Black and B. Das, "Programmable logic using giant-magnetoresistance and spin-dependent tunneling devices," J. Applied Physics, 87(9): 6674--6679, 2000.
[13]
W. Zhao, C. Chappert, V. Javerliac, and J-P Noziere, "High speed, high stability and low power sensing amplifier for mtj/cmos hybrid logic circuits," Magnetics, IEEE Transactions on, 2009.
[14]
H. Koike et al., "A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop," Solid-State Circuits Conference (A-SSCC), IEEE Asian, pp. 317--320, Nov. 2013
[15]
B. Jovanovic, R. M. Brum and L. Torres, "Comparative Analysis of MTJ/CMOS Hybrid Cells based on TAS and In-plane STT Magnetic Tunnel Junctions," Magnetics, IEEE Transactions on, vol. PP, no. 99, pp. 1, 1
[16]
B. Cambou, "Match In Place. A novel way to perform secure and fast user's authentication," available online at www.crocus-technology.com
Index Terms
- Potential applications based on NVM emerging technologies
Recommendations
Emerging NVM: A Survey on Architectural Integration and Research Challenges
There has been a surge of interest in Non-Volatile Memory (NVM) in recent years. With many advantages, such as density and power consumption, NVM is carving out a place in the memory hierarchy and may eventually change our view of computer architecture. ...
Modeling, Architecture, and Applications for Emerging Memory Technologies
Editor's note:Spin-transfer torque RAM and phase-change RAM are vying to become the next-generation embedded memory, offering high speed, high density, and nonvolatility. This article discusses new opportunities and challenges presented by these two ...
NVM duet: unified working memory and persistent store architecture
ASPLOS '14: Proceedings of the 19th international conference on Architectural support for programming languages and operating systemsEmerging non-volatile memory (NVM) technologies have gained a lot of attention recently. The byte-addressability and high density of NVM enable computer architects to build large-scale main memory systems. NVM has also been shown to be a promising ...
Comments
Information & Contributors
Information
Published In
Sponsors
- EDAA: European Design Automation Association
- ECSI
- EDAC: Electronic Design Automation Consortium
- SIGDA: ACM Special Interest Group on Design Automation
- Russian Acadamy of Sciences: Russian Acadamy of Sciences
- IEEE Council on Electronic Design Automation (CEDA)
Publisher
EDA Consortium
San Jose, CA, United States
Publication History
Published: 09 March 2015
Check for updates
Qualifiers
- Research-article
Conference
DATE '15
Sponsor:
- EDAA
- EDAC
- SIGDA
- Russian Acadamy of Sciences
Acceptance Rates
DATE '15 Paper Acceptance Rate 206 of 915 submissions, 23%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%
Upcoming Conference
DATE '25
- Sponsor:
- sigda
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 148Total Downloads
- Downloads (Last 12 months)2
- Downloads (Last 6 weeks)0
Reflects downloads up to 02 Feb 2025
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in