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Low-cost branch folding for embedded applications with small tight loops

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John ArendsAuthors Info & Claims

MICRO 32: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture

Pages 103 - 111

Published: 16 November 1999 Publication History

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Abstract

Many portable and embedded applications are characterized by spending a large fraction of execution time on small program loops. To improve performance, many embeded systems use special instructions to handle program loop executions. These special instructions, however, consume opcode space, which is valuable in the embedded computing environments. In this paper, we propose a hardware technique for folding out branches when executing these small loops. This technique does not require any special branch instructions. It is based on the detection and utilization of certain short backward branch instructions (sbb). A sbb is any PC-relative branch instruction with a limited backward branch distance. Once a sbb is detected, its displacement field is used by the hardware to identify the actual program loop size. It does so by loading this negative displacement field into a counter and incrementing the counter for each instruction sequentially executed. As the count approaches zero, the hardware folds out the sbb by predicting that it is always taken. The hardware overhead for this technique is minimal. Using a 5-bit increment counter, the performance improvement over a set of embedded applications is about 7.5%.

References

[1]

ADSP-2106x SHARCTM User's Manual, Analog Devices Inc., 1998.

[2]

D. Ditzel, H. McLellan, "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero," Proc. IEEE Int'l. Syrup. on Computer Architecture, 1987.

Digital Library

[3]

Kissell, MIPSI6: High-density MIPS for the Embedded Market, Silicon Graphics MIPS Group, 1997.

[4]

M. Kozuch and A. Wolfe, "Compression of Embedded System Programs," Proc. IEEE lnt'l Conf. on Computer Design, 1994.

Digital Library

[5]

J. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design," IEEE Computer, pp.6-22, January 1984.

[6]

B. Moyer, J. Arends, "RISC Gets Small," Byte Magazine, February 1998.

[7]

M. CORE Reference Manual, Motorola Inc., 1997.

[8]

PowerPC 603 RISC Microprocessor User's Manual, IBM Microelectronics/Motorola Incorp., 1990.

[9]

J. Scott, L. H. Lee, J. Arends and B. Moyer, "Designing the Low-Power M.CORE Architecture," Proc. Power Driven Microarchitecture Workshop, Barcelona, Spain, June 28th 1998.

[10]

J. Scott, L. H. Lee, A. Chin, J. Arends and B. Moyer, "Designing the MoCORE M3 CPU Architecture," Proc. IEEE Int'l Conf. on Computer Design, Austin, Texas, October 10- t 3, 1999.

Digital Library

[11]

J.E. Smith, "A Study of Branch Prediction Strategies,' Proc. IEEE lnt'l Syrup. on Comp. Architecture, May 1991.

Digital Library

[12]

SuperH SH-4 Hardware Manual, Hitachi Inc., 1998.

[13]

TMS320C2x User's Guide, Texas Instruments Inc., 1993.

[14]

TriCore Architecture Manual, Siemens Incorp., 1997.

[15]

A. Wolfe and A. Chanin, "Executing Compressed Programs on an Embedded RISC Architecture," Proc. IEEE Int'l Symp. on Microarchitecture, December 1992.

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Cited By

Petrov POrailoglu ARabaey J(2001)Speeding up control-dominated applications through microarchitectural customizations in embedded processorsProceedings of the 38th annual Design Automation Conference10.1145/378239.379014(512-517)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.379014

Index Terms

Low-cost branch folding for embedded applications with small tight loops
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
2. Hardware
  1. Electronic design automation
    1. Methodologies for EDA
  2. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
      2. Design modules and hierarchy

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Information

Published In

cover image ACM Conferences

MICRO 32: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture

November 1999

299 pages

ISBN:076950437X

Chairmen:
Ronny Ronen
Intel Israel
,
Matthew Farrens
Univ. of California, Davis
,
Ilan Spillinger
Intel Israel

Copyright © Copyright (c) 1998 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Sponsors

IEEE TC - MICRO: IEEE TC - MICRO
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

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IEEE Computer Society

United States

Publication History

Published: 16 November 1999

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MICRO99

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IEEE TC - MICRO
SIGMICRO

MICRO99: 32nd Annual ACM/IEEE International Symposium on Microarchitecture

November 16 - 18, 1999

Haifa, Israel

Acceptance Rates

MICRO 32 Paper Acceptance Rate 27 of 131 submissions, 21%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

Petrov POrailoglu ARabaey J(2001)Speeding up control-dominated applications through microarchitectural customizations in embedded processorsProceedings of the 38th annual Design Automation Conference10.1145/378239.379014(512-517)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.379014

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