An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm
Pages 327 - 328
Abstract
The purpose of this article is to introduce a CORDIC-based Arithmetic Processor which utilizes both angle recoding (ARD) and scaling-free (SCFE) CORDIC algorithms. The proposed processor is able to operate the sine, cosine, sine hyperbolic, cosine hyperbolic, and multiplication function. Its hardware architecture implemented in 180 nm CMOS technology is capable of working at 100 MHz frequency and spends 12.96 mW power consumption. In comparison with some previous work, the design is a good choice for high-throughput low-energy applications.
References
[1]
J. E. Volder, IRE Trans. Elec. Compt., Vol. EC-8, pp. 330--334, 1959.
[2]
J.S. Walther, SJCC., pp. 379--385, 1971.
[3]
T. Y. Sung et al., IET Compt. Dig. Tech., pp. 581 - 589, 2007.
[4]
Y. H. Hu et al., IEEE Trans. Compt., Vol.42, pp.99-102, 1993.
[5]
Y. H. Hu et al., IEEE Trans. Sign. Proc., Vol. 43, pp. 331--336, 1995.
[6]
K. Maharatna et al., IET Compt. Dig. Tech., Vol. 151, pp. 448--456, 2004.
[7]
K. Maharatna et al., IEEE TCAS. for Video Tech., Vol. 15, pp. 1463--1474, 2005.
[8]
S. Aggarwal et al., IEEE Trans. VLSI Syst. Vol. 24, pp. 1588--1592, 2016.
[9]
F. J. Jaime et al., IEEE TCAS I, Vol. 57, pp. 1654- 2010.
[10]
J. Zhang et al., IEICE ELEX., Vol. 9, pp. 765- 2012.
- An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm
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- IEEE Circuits and Systems Society
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE Council on Electronic Design Automation (CEDA)
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IEEE Press
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Published: 22 January 2018
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ASPDAC '18
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ASPDAC '18: 23rd Asia and South Pacific Design Automation Conference
January 22 - 25, 2018
Jeju, Republic of Korea
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Overall Acceptance Rate 466 of 1,454 submissions, 32%
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