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View all- Hoffman AKogel TMeyr H(2001)A framework for fast hardware-software co-simulationProceedings of the conference on Design, automation and test in Europe10.5555/367072.367949(760-765)Online publication date: 13-Mar-2001
A system-level co-verification environment for ATM hardware design
Authors: 
G. Post, A. Müller, T. GrötkerAuthors Info & Claims
G. Post, A. Müller, T. GrötkerAuthors Info & ClaimsAbstract
Common approaches to hardware implementation of networking components start at the VHDL level and are based on the creation of regression test benches to perform simulative validation of functionality. The time needed to develop test benches has proven to be a significant bottleneck with respect to time-to-market requirements. In this paper, we describe the coupling of a telecommunication network simulator with a VHDL simulator and a hardware test board. This co-verification approach enables the designer of hardware for networking components to verify the functional correctness of a device under test against the corresponding algorithmic description and to perform functional chip verification by reusing test benches from a higher level of abstraction.
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- A system-level co-verification environment for ATM hardware design
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View all- Hoffman AKogel TMeyr H(2001)A framework for fast hardware-software co-simulationProceedings of the conference on Design, automation and test in Europe10.5555/367072.367949(760-765)Online publication date: 13-Mar-2001
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