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Statistical techniques of timing verification

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James H. Shelly,

David R. TryonAuthors Info & Claims

DAC '83: Proceedings of the 20th Design Automation Conference

Pages 396 - 402

Published: 27 June 1983 Publication History

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Abstract

Timing verification of VLSI designs using statistical techniques such as those implemented in Hitchcock's Timing Analysis¹ permit a far more precise assessment of machine performance than previous techniques. The accuracy of these results is affected by proper user specification of statistical input parameters and by the algorithmic treatment of the system design. Since these items are both system and technology dependent, the system designer must understand them and apply appropriate statistical techniques in order to insure a properly verified design. This paper both outlines the mathematical derivations and illustrates the magnitude of the improvements to be obtained.

References

[1]

R. B. Hitchcock, "Timing Verification and the Timing Analysis Program", Proceedings of the 19th Design Automation Conference, Las Vegas, (pp 594-603), 1982.

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[2]

T. I. Kirkpatrick and N. R. Clark, "PERT as an AID to Logic Design", IBM Journal of Research and Development, Vol. 10, No. 2, (pp 135-141), March 1966.

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[3]

T. M. McWilliams, "Verification of Timing Constraints on Large Digital Systems", Proceedings of the 17th Design Automation Conference, Minneapolis,(pp139-147), 1980.

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Cited By

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Park EMercer MWilliams T(1992)The Total Delay Fault Model and Statistical Delay Fault CoverageIEEE Transactions on Computers10.1109/12.14462141:6(688-698)Online publication date: 1-Jun-1992
https://dl.acm.org/doi/10.1109/12.144621
Park EMercer MWilliams T(1989)A Statistical Model for Delay-Fault TestingIEEE Design & Test10.1109/54.203896:1(45-55)Online publication date: 1-Jan-1989
https://dl.acm.org/doi/10.1109/54.20389
Park EMercer MWilliams T(1988)Statistical delay fault coverage and defect level for delay faultsProceedings of the 1988 international conference on Test: new frontiers in testing10.5555/1896122.1896209(492-499)Online publication date: 12-Sep-1988
https://dl.acm.org/doi/10.5555/1896122.1896209
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Index Terms

Statistical techniques of timing verification
1. Computing methodologies
  1. Machine learning
    1. Machine learning approaches
      1. Factorization methods
        Canonical correlation analysis
2. Mathematics of computing
  1. Probability and statistics
    1. Statistical paradigms
      1. Regression analysis
      2. Time series analysis

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DAC '83: Proceedings of the 20th Design Automation Conference

June 1983

700 pages

ISBN:0818600268

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IEEE Press

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Published: 27 June 1983

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Park EMercer MWilliams T(1992)The Total Delay Fault Model and Statistical Delay Fault CoverageIEEE Transactions on Computers10.1109/12.14462141:6(688-698)Online publication date: 1-Jun-1992
https://dl.acm.org/doi/10.1109/12.144621
Park EMercer MWilliams T(1989)A Statistical Model for Delay-Fault TestingIEEE Design & Test10.1109/54.203896:1(45-55)Online publication date: 1-Jan-1989
https://dl.acm.org/doi/10.1109/54.20389
Park EMercer MWilliams T(1988)Statistical delay fault coverage and defect level for delay faultsProceedings of the 1988 international conference on Test: new frontiers in testing10.5555/1896122.1896209(492-499)Online publication date: 12-Sep-1988
https://dl.acm.org/doi/10.5555/1896122.1896209
Wallace DSéquin CThomas D(1986)Plug-in timing models for an abstract timing verifierProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318140(683-689)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318140
Glesner MSchuck JSteck RThomas D(1986)SCAT—a new statistical timing verifier in a silicon compiler systemProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318048(220-226)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318048
Unger STan C(1986)Clocking Schemes for High-Speed Digital SystemsIEEE Transactions on Computers10.1109/TC.1986.167667935:10(880-895)Online publication date: 1-Oct-1986
https://dl.acm.org/doi/10.1109/TC.1986.1676679
Kelly VLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)The CRITTER systemProceedings of the 21st Design Automation Conference10.5555/800033.800832(419-425)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800832

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Statistical timing verification for transparently latched circuits

Latch modeling for statistical timing analysis

Clock independent timing verification of level-sensitive latches

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Cited By

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Recommendations

Statistical timing verification for transparently latched circuits

Latch modeling for statistical timing analysis

Clock independent timing verification of level-sensitive latches

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