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Test strategy for microprocessers

Authors:

Sunil K. Jain,

Alfred K. SusskindAuthors Info & Claims

DAC '83: Proceedings of the 20th Design Automation Conference

Pages 703 - 708

Published: 27 June 1983 Publication History

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Abstract

We divide microprocessor testing into three distinct phases: verification of the control and data transfer functions; verification of the data-manipulation functions; and verification of the input-output functions. Here we deal in detail only with the first of these.

To verify control, appropriate additional signals inside the chip are used and made observable at the terminal pins of the microprocessor chip. Complete instruction sequences, executed in a test mode, then serve to verify the control functions. Procedures for doing this are given and also for verifying data transfer functions.

References

[1]

N. Tredennick, "How to Flowchart for Hardware", IEEE Computer, 14 (12), Dec. 1981, pp. 87-102.

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Google Scholar

[2]

S. M. Thatte and J.A. Abraham, "Test Generation for Microprocessor", IEEE Transactions on Computers, C-29(6), June 1980, pp. 429-44.

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Google Scholar

[3]

Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill Book Company, New York, 1978.

Digital Library

Google Scholar

[4]

B. Koenemann, J. Mucha, and G. Zwiehoff, "Built-in Logic Block Observation Techniques", Digest 1979 Test Conference, Oct. 1979, pp. 37-41.

Google Scholar

[5]

A. H. Ashkinazy, Fault Detection in Asynchronous Sequential Machines, Ph D Thesis, Columbia University, 1970.

Google Scholar

[6]

H. Fujiwara, Y. Nagao, T. Sasao, K. Kinoshita, "Easily Testable Sequential Machines with Extra Inputs", IEEE Trans. on Computers, C-24(8), Aug. 1975, pp. 821-826.

Digital Library

Google Scholar

[7]

S. K. Jain, "Testable Design of Microprocessors and Other VLSI", M. S. Thesis in Elect. Eng. Lehigh Univ., 1982.

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Shen JAbraham J(1998)Synthesis of Native Mode Self-Test ProgramsJournal of Electronic Testing: Theory and Applications10.1023/A:100830582097913:2(137-148)Online publication date: 1-Oct-1998
https://dl.acm.org/doi/10.1023/A%3A1008305820979
Malaiya Y(1989)On inherent untestability of unaugmented microprogrammed controlACM SIGMICRO Newsletter10.1145/75395.7540520:3(88-96)Online publication date: 1-Aug-1989
https://dl.acm.org/doi/10.1145/75395.75405
Malaiya Y(1989)On inherent untestability of unaugmented microprogrammed controlProceedings of the 22nd annual workshop on Microprogramming and microarchitecture10.1145/75362.75405(88-96)Online publication date: 1-Aug-1989
https://dl.acm.org/doi/10.1145/75362.75405

Index Terms

Test strategy for microprocessers
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. Hardware

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DAC '83: Proceedings of the 20th Design Automation Conference

June 1983

700 pages

ISBN:0818600268

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IEEE Press

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Published: 27 June 1983

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Shen JAbraham J(1998)Synthesis of Native Mode Self-Test ProgramsJournal of Electronic Testing: Theory and Applications10.1023/A:100830582097913:2(137-148)Online publication date: 1-Oct-1998
https://dl.acm.org/doi/10.1023/A%3A1008305820979
Malaiya Y(1989)On inherent untestability of unaugmented microprogrammed controlACM SIGMICRO Newsletter10.1145/75395.7540520:3(88-96)Online publication date: 1-Aug-1989
https://dl.acm.org/doi/10.1145/75395.75405
Malaiya Y(1989)On inherent untestability of unaugmented microprogrammed controlProceedings of the 22nd annual workshop on Microprogramming and microarchitecture10.1145/75362.75405(88-96)Online publication date: 1-Aug-1989
https://dl.acm.org/doi/10.1145/75362.75405

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Instruction-level test methodology for CPU core self-testing

Test Strategy for the PowerPC 750 Microprocessor

A general decomposition strategy for verifying register renaming

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Instruction-level test methodology for CPU core self-testing

Test Strategy for the PowerPC 750 Microprocessor

A general decomposition strategy for verifying register renaming

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