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Automatic PLA synthesis from a DDL-P description

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W. M. vanCleemputAuthors Info & Claims

DAC '81: Proceedings of the 18th Design Automation Conference

Pages 391 - 397

Published: 29 June 1981 Publication History

Abstract

This paper describes an automatic PLA synthesis (APLAS) system which automatically generates a PLA for the control function of a design from a DDL-P description of a digital system. APLAS can also minimize and partition the PLA to meet the design constraints.

This is a very convenient tool for designing finite state machines. The control circuit of any digital system for which a state diagram can be drawn can be designed easily using this system.

References

[1]

S. Kang, Minimization, Partitioning and Synthesis of Programmable Logic Arrays, Ph.D. dissertation, Dept. of EE, Stanford University, to be published.

[2]

S. Kang and W. M. vanCleemput, SALT user's manual, Computer Systems Lab. Tech. Report No. 203, Stanford University, Mar. 1981.

[3]

S. KANG and W. M. vanCleemput, SPAM user's manual, Computer Systems Lab. Tech. Report No. 204, Stanford University, Mar. 1981.

[4]

W. M. vanCleemput, Design automation at Stanford, Computer Systems Lab. Tech. Report No. 178, Stanford University, July 1979.

Digital Library

[5]

W. M. vanCleemput, Design automation at Stanford, Computer Systems Lab. Tech. Report No. 184, Stanford University, Feb. 1980.

Digital Library

[6]

J. R. Duley and D. L. Dietmeyer, "A digital system design language (DDL)," IEEE Trans. Comput., vol. C-17, pp. 850-861, Sept. 1968.

[7]

J. R. Duley and D. L. Dietmeyer, " Translation of a DDL digital system specification to Boolean equations," IEEE Trans. Comput., vol. C-18, pp. 305-313, Apr. 1969.

[8]

R. L. Arndt and D. L. Dietmeyer, "DDLSIM - A digital design language simulator," Proc. National Electronics Conf., vol. 26, pp. 116-118, Dec. 1970.

[9]

W. E. Cory, J. R. Duley and W. M. vanCleemput, An introduction to the DDL-P language, Computer Systems Lab. Tech. Report No. 163, Stanford University, Mar. 1979.

Digital Library

[10]

W. E. Cory,J. R. Duley and W. M. vanCleemput, DDL-P Command Language Manual, Computer Systems Lab. Tech. Report No. 164, Stanford University, Mar. 1979.

Digital Library

[11]

D. B. Armstrong, "A programmed algorithm for assigning internal codes to sequential machines," IRE Trans. Electron. Comput., vol. EC-11, pp. 466-472, Aug. 1962.

[12]

D. B. Armstrong, "On the efficient assignment of internal codes to sequential machines," IRE Trans. Electron. Comput., vol. EC-11, pp. 611-622, Oct. 1962.

[13]

T. A. Dolotta and E. J. McCluskey, "The coding of internal states of sequential circuits," IEEE Trans. Electron. Comput., vol. EC-13, pp. 549-563, Oct. 1964.

[14]

J. R. Story, H. J. Harrison, and E. A. Reinhard, "Optimum state assignment for synchronous sequential circuits," IEEE Trans. Comput., vol. C-21, pp. 1365-1373, Dec. 1972.

[15]

P. Bricaud and J. Campbell, "Multiple output PLA Minimization: EMIN," Wescon 78.

[16]

S. J. Hong, R. G. Cain and D. L. Ostapko, "MINI: A heuristic approach for logic minimization," IBM J. Res. Develop., vol. 18, pp. 443-458, Sept. 1974.

Digital Library

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H. Langenbacher, "Boolean minimization for logic arrays," M. S. Thesis, Dept. of EE, San Diego State Univ., Fall, 1979.

Cited By

Hsu YLin YHsieh HChao T(1991)Combining Logic Minimization and Folding for PLAsIEEE Transactions on Computers10.1109/12.9024940:6(706-713)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1109/12.90249
Goré RRamaamohanarao KThomas D(1989)Automatic synthesis of Boolean equations using programmable array logicProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74430(283-289)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74430
Trevillyan L(1987)An overview of logic synthesis systemsProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.37913(166-172)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.37913
Show More Cited By

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Automatic PLA synthesis from a DDL-P description

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cover image ACM Conferences

DAC '81: Proceedings of the 18th Design Automation Conference

June 1981

899 pages

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

Publication History

Published: 29 June 1981

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Cited By

Hsu YLin YHsieh HChao T(1991)Combining Logic Minimization and Folding for PLAsIEEE Transactions on Computers10.1109/12.9024940:6(706-713)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1109/12.90249
Goré RRamaamohanarao KThomas D(1989)Automatic synthesis of Boolean equations using programmable array logicProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74430(283-289)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74430
Trevillyan L(1987)An overview of logic synthesis systemsProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.37913(166-172)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.37913
Koseki YYamada TOfek HO'Neill L(1985)PLAYERProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317983(766-769)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317983
Ramayya KKumar APrasad SOfek HO'Neill L(1985)An automated data path synthesizer for a canonic structure, implementable in VLSIProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317916(381-387)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317916
Meyer MAgrawal PPfister RLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)A VLSI FSM design systemProceedings of the 21st Design Automation Conference10.5555/800033.800834(434-440)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800834
Lewandowski JLiu CLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)A branch and bound algorithm for optimal pla foldingProceedings of the 21st Design Automation Conference10.5555/800033.800833(426-433)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800833
Papachriston CReuter JCarter MMueller R(1984)Microassembly and area reduction techniques for PLA microcodeProceedings of the 17th annual workshop on Microprogramming10.1145/800016.808218(86-94)Online publication date: 1-Dec-1984
https://dl.acm.org/doi/10.1145/800016.808218
Papachriston CReuter J(1984)Microassembly and area reduction techniques for PLA microcodeACM SIGMICRO Newsletter10.1145/384281.80821815:4(86-94)Online publication date: 1-Dec-1984
https://dl.acm.org/doi/10.1145/384281.808218
Sasao T(1984)Input Variable Assignment and Output Phase Optimization of PLA'sIEEE Transactions on Computers10.1109/TC.1984.167634933:10(879-894)Online publication date: 1-Oct-1984
https://dl.acm.org/doi/10.1109/TC.1984.1676349
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