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Analytical power/timing optimization technique for digital system

Authors:

A. E. Ruehli,

P. K. Wolff,

G. GoertzelAuthors Info & Claims

DAC '77: Proceedings of the 14th Design Automation Conference

Pages 142 - 146

Published: 01 January 1977 Publication History

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Abstract

A method for logic gate delay assignment is described which achieves power minimization of digital logic while satisfying system timing. The logic gates are described by a single design parameter macromodel. A Newton optimization scheme is employed using exact sparse updating. Systems consisting of up to 1200 digital logic gates have been optimized. A companion paper describes how a further optimization of the system is achieved if power-oriented placement improvement is included in the optimization procedure.

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B. J. Agule, J. D. Lesser, A. E. Ruehli, P. K. Wolff, Sr., "An Experimental System for Power/Timing Optimization of LSI Chips", 14th Design Automation Conference, June 20,21,22, 1977, New Orleans, Louisiana.

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Markov IHu JKim MHu A(2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429441
Kim MMarkov IGroeneveld PSciuto DHassoun S(2012)ComPLx: A Competitive Primal-dual Lagrange Optimization for Global PlacementProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228496(747-752)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228496
Nikoubin TBahrebar PPouri SNavi KIravani V(2010)Simple exact algorithm for transistor sizing of low-power high-speed arithmetic circuitsVLSI Design10.1155/2010/2643902010(1-7)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/264390
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Analytical power/timing optimization technique for digital system

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The minimization of power consumption is an important design constraint for circuits used in portable devices. The s itching activity of a circuit node in a CMOS digital circuit directly contributes to overall power dissipation. By approximating the ...

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DAC '77: Proceedings of the 14th Design Automation Conference

January 1977

507 pages

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Published: 01 January 1977

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Markov IHu JKim MHu A(2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429441
Kim MMarkov IGroeneveld PSciuto DHassoun S(2012)ComPLx: A Competitive Primal-dual Lagrange Optimization for Global PlacementProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228496(747-752)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228496
Nikoubin TBahrebar PPouri SNavi KIravani V(2010)Simple exact algorithm for transistor sizing of low-power high-speed arithmetic circuitsVLSI Design10.1155/2010/2643902010(1-7)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/264390
Ayupov AMarchenko ATiourin VNarayanan VYan ZMacii EBhanja S(2008)An analytical approach to placement legalizationProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366152(167-170)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366152
Hentschke RNarasimhan JKung DGalup-Montoro CBampi SOrailoglu A(2005)Improving run times by pruned application of synthesis transformsProceedings of the 18th annual symposium on Integrated circuits and system design10.1145/1081081.1081098(38-43)Online publication date: 4-Sep-2005
https://dl.acm.org/doi/10.1145/1081081.1081098
Coudert O(1996)Gate SizingProceedings of the 1996 European conference on Design and Test10.5555/787259.787597Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787597
Coudert OHaddad RHorowitz MRabaey JBarton BPedram M(1996)Integrated resynthesis for low powerProceedings of the 1996 international symposium on Low power electronics and design10.5555/252493.252596(169-174)Online publication date: 12-Aug-1996
https://dl.acm.org/doi/10.5555/252493.252596
Coudert OHaddad RManne SPennino TYoffa E(1996)New algorithms for gate sizingProceedings of the 33rd annual Design Automation Conference10.1145/240518.240658(734-739)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240658
Onozawa AKitazawa HKawai K(1995)Post-layout optimization of power and timing for ECL LSIsProceedings of the 1995 European conference on Design and Test10.5555/787258.787407Online publication date: 6-Mar-1995
https://dl.acm.org/doi/10.5555/787258.787407
Chan PSmith R(1991)Algorithms for library-specific sizing of combinational logicProceedings of the 27th ACM/IEEE Design Automation Conference10.1145/123186.123302(353-356)Online publication date: 3-Jan-1991
https://dl.acm.org/doi/10.1145/123186.123302
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An experimental system for power/timing optimization of LSI chips

Post-layout optimization of power and timing for ECL LSIs

Low power optimization technique for BDD mapped circuits

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