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Article

Improved Symoblic Simulation by Dynamic Funtional Space Partitioning

Published: 16 February 2004 Publication History

Abstract

In this paper, we provide a flexible and automatic method to partition the functional space for efficient symbolic simulation. We utilize a 2-tuple list representation as the basis for partitioning the functional space. The partitioning is carried out dynamically during the symbolic simulation based on the sizes of OBDDs. We develop heuristics for choosing the optimal partitioning points. These heuristics intend to balance the tradeoff between the time and space complexity. We demonstrate the effectiveness of our new symbolic simulation approach through experiments based on a floating point adder and a memory management unit.

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{3} Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger. Formal Verification Using Parametric Representations of Boolean Constraints. In 36th ACM/IEEE Design Automation Conference, 1999.
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{4} Amit Narayan, Jawahar Jain, Fujita, Sangiovanni. Paritioned ROBDDs - A Compact, Canonical and Efficiently Manipulable Representation for Boolean Functions. In ACM/IEEE Int. Conference on Computer-Aided Design, 1996.
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{5} R. E. Bryant. On the Complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. In IEEE Trans. on Computer, 1991.
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{6} T. Feng, Li-C. Wang, Kwang-Ting Cheng Improved Symbolic Simulation By Functional Space Decomposition. In Asia and South Pacific Design Automation Conference, 2004.
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{7} K. C. Chang. Digital Systems Design with VHDL and Synthesis, An integrated approach. In IEEE computer society press, 1999.
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{8} T. Feng, Li-C. Wang, Kwang-Ting Cheng etc Enhanced Symbolic Simulation for Efficient Verification of Embedded Array Systems. In Asia and South Pacific Design Automation Conference, 2003.
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{9} Yirng-An Chen, Randal E. Bryant Verification of Floating Point Adders In Proceeding of International Conference of Computer Aided Verification, 1998.
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{10} D. J. Smith Practical Modeling Examples - HDL Chip Design In Doone Publications, Chapter 12, 1996.

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cover image ACM Conferences
DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1
February 2004
688 pages
ISBN:0769520855

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IEEE Computer Society

United States

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Published: 16 February 2004

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