article

Free access

HPS, a new microarchitecture: rationale and introduction

Authors:

Y. N. Patt,

W. M. Hwu,

M. ShebanowAuthors Info & Claims

ACM SIGMICRO Newsletter, Volume 16, Issue 4

Pages 103 - 108

https://doi.org/10.1145/18906.18916

Published: 01 December 1985 Publication History

PDF eReader

Abstract

HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale for its selection, and describes the data path and flow of instructions through the microengine.

References

[1]

Anderson, D. W., Sparacio, F. J., Tomasulo, R. M., "The IBM Systed360 Model 91: Machine Philosophy and Instruction - Handling," IBM Journal of Research and Development, Vol. 11, No. 1, 1967, pp. 8-24.

Digital Library

Google Scholar

[2]

Arvind and Goostelow, K. P., "A New Interpreter for Dataflow and Its Implications for Computer Architecture," Department of Information and Computer Science, University of California, Irvine, Tech. Report 72, October 1975.

Google Scholar

[3]

Dennis, J. B., and Misunas, D. P., "A Preliminary Architecture for a Basic Data Flow Processor," Proceedings of the Second International Symposium on Computer Architecture, 1975, pp 126-132.

Digital Library

Google Scholar

[4]

Gajski, D., Kuck, D., Lawrie, D., Sameh, A., "CEDAR -- A Large Scale Multiprocessor," Computer Architecture News, March 1983.

Digital Library

Google Scholar

[5]

Keller, R. M., "Look Ahead Processors," Computing Surveys, vol. 7, no. 4, Dec. 1975.

Digital Library

Google Scholar

[6]

Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol. 11, 1967, pp 25 - 33. Principles and Examples, McGraw-Hill, 1982.

Digital Library

Google Scholar

[7]

Patt, Y.N., Melvin, SW., Hwu, W., and Shebanow, MC., "Critical Issues Regarding HPS, a High Performance Microarchitecture, Proceedings of the 18th International Microprogramming Workshop, Asilomar, CA, December, 1985.

Digital Library

Google Scholar

Cited By

View all

Goossens BGoossens B(2023)Building a RISC-V Processor with a Multiple Hart PipelineGuide to Computer Processor Architecture10.1007/978-3-031-18023-1_10(301-351)Online publication date: 26-Jan-2023
https://doi.org/10.1007/978-3-031-18023-1_10
Tan YChen BZhu LWu QZou PLi Y(2021)On-demand cut off the covert channel to mitigate meltdownScience China Information Sciences10.1007/s11432-018-9678-864:9Online publication date: 27-May-2021
https://doi.org/10.1007/s11432-018-9678-8
Hassan HPekhimenko GVijaykumar NSeshadri VLee DErgin OMutlu O(2016)ChargeCache: Reducing DRAM latency by exploiting row access locality2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446096(581-593)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446096
Show More Cited By

Index Terms

HPS, a new microarchitecture: rationale and introduction

Recommendations

HPS, a new microarchitecture: rationale and introduction
MICRO 18: Proceedings of the 18th annual workshop on Microprogramming

HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale ...
Microarchitecture of HaL's CPU
COMPCON '95: Proceedings of the 40th IEEE Computer Society International Conference

The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order ...
Microarchitecture of the Godson-2 processor

The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that ...

Comments

Information & Contributors

Information

Published In

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 1985

Published in SIGMICRO Volume 16, Issue 4

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

131
Total Citations
View Citations
2,455
Total Downloads

Downloads (Last 12 months)250
Downloads (Last 6 weeks)24

Reflects downloads up to 14 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Goossens BGoossens B(2023)Building a RISC-V Processor with a Multiple Hart PipelineGuide to Computer Processor Architecture10.1007/978-3-031-18023-1_10(301-351)Online publication date: 26-Jan-2023
https://doi.org/10.1007/978-3-031-18023-1_10
Tan YChen BZhu LWu QZou PLi Y(2021)On-demand cut off the covert channel to mitigate meltdownScience China Information Sciences10.1007/s11432-018-9678-864:9Online publication date: 27-May-2021
https://doi.org/10.1007/s11432-018-9678-8
Hassan HPekhimenko GVijaykumar NSeshadri VLee DErgin OMutlu O(2016)ChargeCache: Reducing DRAM latency by exploiting row access locality2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446096(581-593)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446096
Yazdanpanah FAlvarez-Martinez CJimenez-Gonzalez DEtsion Y(2014)Hybrid Dataflow/von-Neumann ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.12525:6(1489-1509)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1109/TPDS.2013.125
Palem KKathail VTatge RBarua R(2010)Compilers, architectures and synthesis for embedded computingProceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1878921.1878947(167-176)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878921.1878947
Chang PHao EPatt YChang P(1996)Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative ExecutionInternational Journal of Parallel Programming10.1007/BF0335674924:3(209-234)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1007/BF03356749
Bera RRanganathan ARakshit JMahto SNori AGaur JOlgun AKanellopoulos KSadrosadati MSubramoney SMutlu O(2024)Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00017(88-102)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00017
Elsabbagh FSheikhha SYing VNguyen QEmer JSanchez D(2023)Accelerating RTL Simulation with Hardware-Software Co-DesignProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614257(153-166)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614257
Voitsechov DPort OEtsion YOskin MInoue K(2018)Inter-thread communication in multithreaded, reconfigurable coarse-grain arraysProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00013(42-54)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00013
Ghose SHsieh KBoroumand AAusavarungnirun RMutlu O(2018)The Processing-in-Memory Paradigm: Mechanisms to Enable AdoptionBeyond-CMOS Technologies for Next Generation Computer Design10.1007/978-3-319-90385-9_5(133-194)Online publication date: 21-Aug-2018
https://doi.org/10.1007/978-3-319-90385-9_5
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Abstract

References

Cited By

Index Terms

Recommendations