IEICE Trans - A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

Tohru KANEKO
Koji HIROSE
Akira MATSUZAWA

Publication
IEICE TRANSACTIONS on Electronics Vol.E101-C No.4 pp.224-232
Publication Date: 2018/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.224
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
current mirror, CMOS, calibration, body bias control,

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Summary:
A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.