IEICE Trans - Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults

Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults

Yukihiro SASAGAWA
Jun YAO
Yasuhiko NAKASHIMA

Publication
IEICE TRANSACTIONS on Information and Systems Vol.E97-D No.12 pp.3083-3091
Publication Date: 2014/12/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2014PAP0024
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword:
adaptive redundancy, setup error recovery, DVS, low power, AVF, ILP,

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Summary:
Razor Flip-Flop (FF) is a good combination for the dynamic voltage scaling (DVS) technique to achieve high energy efficiency. We previously proposed a RazorProtector scheme, which uses, under a very high IR-drop zone, a redundant data-path to provide a very fast recovery for a Razor-FF based processor. In this paper, we propose a dynamic method to adjust the redundancy level to fine-grained fit both the program behaviors and processor manufacturing variations so as to achieve an optimal power saving. We design an online turning method to adjust the redundancy level according to the most related parameters, ILP (Instruction Level Parallelism) and DCF (Delay Criticality Factor). Our simulation results show that under a workload suite with different behaviors, the adaptive redundancy can achieve better Energy Delay Product (EDP) reduction than any static controls. Compared to the traditional application of Razor-FF and DVS, our proposed dynamic control achieves an EDP reduction of 56% in average for the workloads we studied.

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