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Maurizio Palesi

Associate Professor of Computer Engineering (google scholar)
University of Catania, Italy
maurizio.palesi@unict.it

Short bio

Maurizio Palesi is an Associate Professor in the Department of Electrical, Electronics, and Computer Engineering at the University of Catania, Member of the ACM and a Senior Member of the IEEE. He earned his Ph.D. from the University of Catania in 2003.

Dr. Palesi's research primarily focuses on the design, optimization, and evaluation of advanced computing architectures, particularly in the fields of multi-core systems and network-on-chip (NoC) technologies. His work investigates efficient communication and data routing strategies within NoC architectures, aiming to improve performance, reduce latency, and enhance energy efficiency. He has made significant contributions to dynamic and adaptive routing algorithms, fault tolerance mechanisms, and the integration of artificial intelligence to optimize system functionality. His research also extends to system-level design methodologies and optimization tools for embedded systems and parallel computing, addressing both theoretical models and practical implementations. Across his body of work, Dr. Palesi consistently emphasizes scalability, reliability, and power efficiency in modern computational infrastructures.

Dr. Palesi has co-authored over 190 papers on topics including networks-on-chip (NoC), emerging interconnect technologies, low-power techniques, design space exploration methodologies, approximate computing, and deep neural network (DNN) hardware accelerators. His research on NoC architectures, particularly in routing algorithms, is widely recognized, and he has co-edited a book on the subject, published by Springer. He is also a co-developer of Noxim, one of the most widely used open-source NoC simulators in the research community, which has been cited in approximately 600 papers. Dr. Palesi has served as the Principal Investigator for numerous national and international research projects.

He has been a Guest Editor for over 20 special issues in international journals and has served as General Chair and Technical Program Committee (TPC) Co-Chair for several international conferences and workshops. Additionally, he serves as an Associate Editor for several journals. Dr. Palesi has received several prestigious awards, including the Best Paper Award at DATE 2011 and the HiPEAC Paper Award in 2014.

Publications

Books

  1. Maurizio Palesi and Masoud Daneshtalab. Routing Algorithms in Networks-on-Chip. Springer. ISBN 978-1-4614-8273-4

Journals

  1. A. Das, M. Palesi, J. Kim and P. P. Pande, "Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific and Quantum Computing Systems - Overview, Challenges and Opportunities," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, doi: 10.1109/JETCAS.2024.3445829.
  2. Abhijit Das, Enrico Russo, Maurizio Palesi, “Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators”, IEEE Transactions on Computers, vol. 73, no. 8, pp. 1883-1898, Aug. 2024, doi: 10.1109/TC.2024.3386067.
  3. Grazia V. Aiosa, Maurizio Palesi, Francesca Sapuppo, “EXplainable AI for Decision Support to Obesity Comorbidities Diagnosis”, in IEEE Access, vol. 11, pp. 107767-107782, 2023, doi: 10.1109/ACCESS.2023.3320057
  4. Minging Tang, Enrico Russo, and Maurizio Palesi, “The Position-Based Compression Techniques for DNN Model”, Journal of Supercomputing 79, 17445–17474 (2023). https://doi.org/10.1007/s11227-023-05339-4
  5. E. Russo, M. Palesi, D. Patti, S. Monteleone, G. Ascia and V. Catania, "Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators," in IEEE Internet of Things Journal, vol. 10, no. 2, pp. 1800-1812, 15 Jan.15, 2023, doi: 10.1109/JIOT.2022.3209401
  6. C. Chen, J. Yin, Y. Peng, M. Palesi, W. Cao, L. Huang, A. K. Singh, H. Zhi, X. Wang. Design Challenges of Intra- and Inter- Chiplet Interconnection, IEEE Design & Test 2022, DOI: 10.1109/MDAT.2022.3203005
  7. Das, Abhijit; Kumar, Abhishek; Jose, John; Palesi, Maurizio. Revising NoC in Future Multi-Core based Consumer Electronics for Performance. IEEE CONSUMER ELECTRONICS MAGAZINE, 2021, DOI: 10.1109/MCE.2021.3062001
  8. Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Mineo, A.; Ascia, G.; Catania, V.. DNN Model Compression for IoT Domain Specific Hardware Accelerators. IEEE INTERNET OF THINGS JOURNAL, 2021, DOI: 10.1109/JIOT.2021.3111723
  9. Das, A.; Kumar, A.; Jose, J.; Palesi, M.. Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. IEEE TRANSACTIONS ON COMPUTERS, 2021, DOI: 10.1109/TC.2021.3069968
  10. Dahir, N; Karkar, A; Palesi, M; Mak, T; Yakovlev, A. Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. INTEGRATION, Elsevier, vol. 81, 2021, DOI: 10.1016/j.vlsi.2021.08.008
  11. Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J.; Salerno, V. M.. Exploiting data resilience in wireless network-on-chip architectures. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, vol. 16, no. 2, 2020, DOI: 10.1145/3379448
  12. Deb, Dipika; Jose, John; Palesi, Maurizio. COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, vol. 26, no. 3, 2020, DOI: 10.1145/3428149
  13. Monemi, A.; Khunjush, F.; Palesi, M.; Sarbazi-Azad, H.. An Enhanced DynamicWeighted Incremental Technique for QoS Support in NoC. ACM TRANSACTIONS ON PARALLEL COMPUTING, vol. 7, no. 2, 2020, DOI: 10.1145/3391442
  14. Mnejja, S.; Aydi, Y.; Abid, M.; Monteleone, S.; Catania, V.; Palesi, M.; Patti, D.. Delta multi-stage interconnection networks for scalable wireless on-chip communication. ELECTRONICS, vol. 9, no. 6, 2020, DOI: 10.3390/electronics9060913
  15. Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.. Impact of Users' Beliefs in Text-Based Linguistic Interaction. IEEE ACCESS, vol. 8, 2020, DOI: 10.1109/ACCESS.2020.2978977
  16. Chen, K. -C.; Ebrahimi, M.; Palesi, M.; Kogel, T.. Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators. IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, vol. 10, no. 3, 2020, DOI: 10.1109/JETCAS.2020.3023568
  17. Nabavinejad, S. M.; Baharloo, M.; Chen, K. -C.; Palesi, M.; Kogel, T.; Ebrahimi, M.. An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators. IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, vol. 10, no. 3, 2020, DOI: 10.1109/JETCAS.2020.3022920
  18. Xiao, S.; Wang, X.; Palesi, M.; Singh, A.; Wang, L.; Mak, T.. On Performance Optimization and Quality Control for Approximate-communication-enabled Networks-on-Chip. IEEE TRANSACTIONS ON COMPUTERS, 2020, DOI: 10.1109/TC.2020.3027182
  19. Lahdhiri, Habiba; Lorandel, Jordane; Monteleone, Salvatore; Bourdel, Emmanuelle; Palesi, Maurizio. Framework for Design Exploration and Performance Analysis of RF-NoC Manycore Architecture. JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, vol. 10, no. 4, 2020, DOI: 10.3390/jlpea10040037
  20. Deb, D.; Jose, J.; Palesi, M.. ECAP: Energy-efficient caching for prefetch blocks in tiled chip multiprocessors. IET COMPUTERS & DIGITAL TECHNIQUES, vol. 13, no. 6, 2019, DOI: 10.1049/iet-cdt.2019.0035
  21. Khan, Sarzamin; Anjum, Sheraz; Gulzari, Usman Ali; Ishmanov, Farruh; Palesi, Maurizio; Afzal, Muhammad Khalil. An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks. APPLIED INTELLIGENCE, vol. 48, no. 12, 2018, DOI: 10.1007/s10489-018-1246-7
  22. Tang, Minghua; Lin, Jin; Palesi, Maurizio. The Suboptimal Routing Algorithm for 2D Mesh Network. IEEE TRANSACTIONS ON COMPUTERS, vol. 67, no. 5, 2018, DOI: 10.1109/TC.2017.2775643
  23. Catania, Vincenzo; Mineo, Andrea; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide. Improving Energy Efficiency in Wireless Network-on-Chip Architectures. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, vol. 14, no. 1, 2017, DOI: 10.1145/3138807
  24. Monemi, Alireza; Ooi, Chia Yee; Palesi, Maurizio; Marsono, Muhammad N.. Ping-lock round robin arbiter. MICROELECTRONICS JOURNAL, vol. 63, 2017, DOI: 10.1016/j.mejo.2017.03.004
  25. Monemi, A.; Tang, J. W.; Palesi, M.; Marsono, M. N.. ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform. MICROPROCESSORS AND MICROSYSTEMS, vol. 54, 2017, DOI: 10.1016/j.micpro.2017.08.007
  26. Catania, Vincenzo; Mineo, A; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide. Cycle-accurate network on chip simulation with Noxim. ACM TRANSACTIONS ON MODELING AND COMPUTER SIMULATION, vol. August 2016, no. 1, 2016, DOI: 10.1145/2953878
  27. Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Pande, P; Catania, Vincenzo. On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 35, no. 11, 2016, DOI: 10.1109/TCAD.2016.2524556
  28. Tang, Minghua; Lin, Xiaola; Palesi, Maurizio. The Repetitive Turn Model for Adaptive Routing. IEEE TRANSACTIONS ON COMPUTERS, vol. 66, no. 1, 2016, DOI: 10.1109/TC.2016.2564961
  29. Tang, Minghua; Lin, Xiaola; Palesi, Maurizio. Local Congestion Avoidance in Network-on-Chip. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol. 27, no. 7, 2016, DOI: 10.1109/TPDS.2015.2474375
  30. Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo. Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 24, no. 4, 2016, DOI: 10.1109/TVLSI.2015.2449275
  31. Palesi, M.; Collotta, M.; Daneshtalab, M.; Bose, P.. Special issue on energy efficient methods and systems in the emerging cloud era [Editoriale]. JOURNAL OF COMPUTER AND SYSTEM SCIENCES, vol. 82, no. 2, 2016, DOI: 10.1016/j.jcss.2015.11.006
  32. Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo. Exploiting antenna directivity in wireless NoC architectures. MICROPROCESSORS AND MICROSYSTEMS, vol. 43, 2016, DOI: 10.1016/j.micpro.2016.01.019
  33. Bakhouya, Mohamed; Daneshtalab, Masoud; Palesi, Maurizio; Ghasemzadeh, Hassan. Many-core System-on-Chip: architectures and applications. MICROPROCESSORS AND MICROSYSTEMS, vol. 43, 2016, DOI: 10.1016/j.micpro.2016.05.002
  34. Jafarzadeh, Nima; Palesi, Maurizio; Eskandari, Saeedeh; Hessabi, Shaahin; Afzali Kusha, Ali. Low Energy yet Reliable Data Communication Scheme for Networks on Chip. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 34, no. 12, 2015, DOI: 10.1109/TCAD.2015.2440311
  35. Tang, Minghua; Lin, Xiaola; Palesi, Maurizio. An Offline Method for Designing Adaptive Routing Based on Pressure Model. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 34, no. 2, 2015, DOI: 10.1109/TCAD.2014.2379649
  36. Tang, M.; Lin, X.; Palesi, Maurizio. Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol. 26, no. 3, 2015, DOI: 10.1109/TPDS.2013.184
  37. Palesi, Maurizio; Patti, Davide; Ascia, Giuseppe; Panno, Daniela Giovanna Anna; Catania, Vincenzo. Coupling routing algorithm and data encoding for low power Networks on Chip. JOURNAL OF COMPUTER SCIENCE, vol. 11, no. 3, 2015, DOI: 10.3844/jcssp.2015.552.566
  38. Palesi, Maurizio; Collotta, Mario; Mineo, Andrea; Catania, Vincenzo. An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures. JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, vol. 5, no. 2, 2015, DOI: 10.3390/jlpea5020038
  39. Rusli M., S; Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Yee O., C; Marsono, M. N.. A closed loop power manager for transmission power control in wireless network-on-chip architectures. JURNAL TEKNOLOGI, vol. 75, no. 3, 2015, DOI: 10.11113/jt.v75.3813
  40. Daneshtalab, Masoud; Palesi, Maurizio; Mak, Terrence. Introduction to the special issue on NoC-based many-core architectures. COMPUTERS & ELECTRICAL ENGINEERING, vol. 45, 2015, DOI: 10.1016/j.compeleceng.2015.07.010
  41. Shen, Fangyang; Liu, Lingjia; Palesi, Maurizio. Introduction to the special issue on “Emerging research in Internet of Things”. COMPUTERS & ELECTRICAL ENGINEERING, vol. 44, 2015, DOI: 10.1016/j.compeleceng.2015.05.016
  42. Wang, X; Yang, M; Jiang, Y; Liu, P; Daneshtalab, M; Palesi, M; Mak, T. On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, vol. 13, no. 2 suppl, 2014, DOI: 10.1145/2544375.2544393
  43. Daneshtalab, M.; Palesi, Maurizio; Plosila, J.; Hemani, A.. Editorial of the Special issue on Many-core Embedded Systems. MICROPROCESSORS AND MICROSYSTEMS, vol. 38, no. 6, 2014, DOI: 10.1016/j.micpro.2014.07.002
  44. Catania, Vincenzo; Patti, Davide; Palesi, Maurizio; Spadaccini, A; Fazzino, F.. An open and platfom-independent instruction-set simulator for teaching computer architecture. WSEAS TRANSACTIONS ON INFORMATION SCIENCE AND APPLICATIONS, 2014
  45. Palesi, Maurizio; Stefanov, T.. Special Section on ESTIMedia’13. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, vol. 13, 2014, DOI: 10.1145/2567942
  46. Daneshtalab, M; Palesi, M.; Plosila, J.. Editorial: Special issue on design challenges for many-core processors. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, vol. 13, 2014, DOI: 10.1145/2567941
  47. Daneshtalab, Masoud; Palesi, Maurizio; Mak, Terrence. Introduction to the Special Issue on Network-on-Chip Architectures. COMPUTERS & ELECTRICAL ENGINEERING, vol. 40, 2014, DOI: 10.1016/j.compeleceng.2014.11.005
  48. Jafarzadeh, N.; Palesi, Maurizio; Khademzadeh, A.; Afzali Kusha, A.. Data Encoding Techniques for Reducing Energy Consumption in Networks on Chip. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, DOI: 10.1109/TVLSI.2013.2251020
  49. Mak, T.; Palesi, Maurizio; Daneshtalab, M.. Special issue on emerging on-chip networks and architectures [Editorial]. IET COMPUTERS & DIGITAL TECHNIQUES, vol. 7, no. 6, 2013, DOI: 10.1049/iet-cdt.2013.0144
  50. Wang, X.; Liu, P.; Yang, M.; Palesi, Maurizio; Jiang, Y.; Huang, M. C.. Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2013, DOI: 10.1007/s11390-013-1312-x
  51. Wang, X.; Yang, M.; Jiang, Y.; Palesi, Maurizio; Liu, P.; Mak, T.; Bagherzadeh, N.. Efficient multicast schemes for 3-D Networks-on-Chip. JOURNAL OF SYSTEMS ARCHITECTURE, vol. 59, no. 9, 2013, DOI: 10.1016/j.sysarc.2013.06.002
  52. Shen, F.; Yang, M.; Palesi, Maurizio. Guest Editors’ Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support. PARALLEL COMPUTING, 2013, DOI: 10.1016/j.parco.2013.08.001
  53. Cardo José, Flich; Palesi, Maurizio. Introduction to the special section on on-chip and off-chip network architectures. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, vol. 12, 2013, DOI: 10.1145/2485984.2485992
  54. Chen, J.; Palesi, Maurizio. Introduction to the special section on ESTIMedia'12. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, vol. 12, 2013, DOI: 10.1145/2435227.2435228
  55. Shen, F.; Yang, M.; Palesi, Maurizio. Emerging Computing Architectures and Systems. COMPUTERS & ELECTRICAL ENGINEERING, vol. 38, no. 3, 2012, DOI: 10.1016/j.compeleceng.2012.03.016
  56. Tornero, R.; Orduna, J. M.; Palesi, M.; Duato, J.. A topology-independent mapping technique for application-specific networks-on-chip. COMPUTING AND INFORMATICS, vol. 31, no. 5, 2012
  57. Patti, Davide; Spadaccini, A.; Palesi, Maurizio; Fazzino, F.; Catania, Vincenzo. Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE TRANSACTIONS ON EDUCATION, vol. 55, no. 3, 2012, DOI: 10.1109/TE.2011.2180530
  58. R., Al Dujaily; T., Mak; F., Xia; A., Yakovlev; Palesi, Maurizio. Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol. 23, no. 7, 2012, DOI: 10.1109/TPDS.2011.275
  59. Palesi, Maurizio; Tornero, R.; Orduna, J. M.; Panno, Daniela Giovanna Anna; Catania, Vincenzo. Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. JOURNAL OF UNIVERSAL COMPUTER SCIENCE, vol. 18, no. 7, 2012, DOI: 10.3217/jucs-018-07-0937
  60. Ascia, Giuseppe; Catania, Vincenzo; Di Nuovo, Ag; Palesi, Maurizio; Patti, Davide. Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. APPLIED SOFT COMPUTING, vol. 11, no. 1, 2011, DOI: 10.1016/j.asoc.2009.11.029
  61. Palesi, Maurizio; Ascia, Giuseppe; Fazzino, F; Catania, Vincenzo. Data Encoding Schemes in Networks on Chip. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 30, no. 5, 2011, DOI: 10.1109/TCAD.2010.2098590
  62. Palesi, Maurizio; S., Kumar; R., Marculescu. Network-on-chip architectures and design methodologies. MICROPROCESSORS AND MICROSYSTEMS, vol. 35, no. 2, 2011, DOI: 10.1016/j.micpro.2011.01.002
  63. Palesi, Maurizio; Kumar, S; Catania, Vincenzo. Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 29, 2010, DOI: 10.1109/TCAD.2010.2041851
  64. M., Yang; Y., Jiang; P., Liu; Palesi, Maurizio. Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures. INTERNATIONAL JOURNAL OF HIGH PERFORMANCE SYSTEMS ARCHITECTURE, vol. 2, no. 3/4, 2010
  65. Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, Vincenzo. Application Specific Routing Algorithms for Networks on Chip. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol. 20, 2009, DOI: 10.1109/ASPDAC.2011.5722232
  66. Mejia, A; Palesi, Maurizio; Flich, J; Kumar, S; Lopez, P; Holsmark, R; Duato, J.. Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 17, 2009, DOI: 10.1109/TVLSI.2008.2012010
  67. Palesi, Maurizio; Kumar, S; Catania, Vincenzo. Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms. IET COMPUTERS & DIGITAL TECHNIQUES, vol. 3, 2009, DOI: 10.1049/iet-cdt.2008.0082
  68. Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, vol. 5, no. 2, 2008, DOI: 10.1145/1400112.1400116
  69. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE TRANSACTIONS ON COMPUTERS, vol. 57, 2008, DOI: 10.1109/TC.2008.38
  70. R., Holsmark; Palesi, Maurizio; S., Kumar. Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions. JOURNAL OF SYSTEMS ARCHITECTURE, vol. 54, no. 3-4, 2008, DOI: 10.1016/j.sysarc.2007.07.005
  71. Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario. JOURNAL OF CIRCUITS, SYSTEMS, AND COMPUTERS, vol. 16, 2007, DOI: 10.1142/S0218126607003915
  72. Ascia, Giuseppe; Catania, Vincenzo; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide. Efficient Design Space Exploration for Application Specific Systems-on-a-Chip. JOURNAL OF SYSTEMS ARCHITECTURE, vol. 53, 2007, DOI: 10.1016/j.sysarc.2007.01.004
  73. Bertozzi, D; Kumar, S; Palesi, Maurizio. Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI DESIGN, vol. 2007, 2007, DOI: 10.1155/2007/26454
  74. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. JOURNAL OF UNIVERSAL COMPUTER SCIENCE, vol. 12, 2006, DOI: 10.3217/jucs-012-04-0370
  75. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Improving Wormhole Adaptive Routing in Networks on Chip. WSEAS TRANSACTIONS ON COMPUTERS, vol. 5, 2006
  76. DI NUOVO, A.; Catania, Vincenzo; Palesi, Maurizio. Genetic Learning of a Fuzzy C-Means Classifier System. WSEAS TRANSACTIONS ON INFORMATION SCIENCE AND APPLICATIONS, vol. 3 (9), 2006
  77. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A.. Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach. IEE PROCEEDINGS. COMPUTERS AND DIGITAL TECHNIQUES, vol. 152, no. 6, 2005, DOI: 10.1049/ip-cdt:20045174
  78. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 24, no. 4, 2005, DOI: 10.1109/TCAD.2005.844118
  79. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. Mapping Cores on Network-on-Chip. INTERNATIONAL JOURNAL OF COMPUTATIONAL INTELLIGENCE RESEARCH, vol. 1, no. 1-2, 2005
  80. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms. IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, vol. 8, no. 4, 2004, DOI: 10.1109/TEVC.2004.826389
  81. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Sarta, D.. An Instruction-Level Power Analysis Model with Data Dependency. VLSI DESIGN, vol. 12, 2001, DOI: 10.1155/2001/82129

Book Chapters

  1. M. Daneshtalab, M. Palesi. Basic Concepts on On-Chip Networks. In Routing Algorithms in Networks-on-Chip. Springer. 2013
  2. R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, and M. Palesi. Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip. Springer. 2013
  3. M. Palesi, R. Holsmark, S. Kumar, and V. Catania. Application Specific Routing Algorithms for Low Power Network on Chip Design. Low Power Networks-on-Chip, Springer.
  4. G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, and D. Patti. Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded Systems. Multi-Objective Optimization in Computational Intelligence: Theory and Practice. Lam Thu Bui (editor), Sameer Alam (editor), Chapter X, pp. 265-299, 2008.
  5. G. Ascia, V. Catania, and M. Palesi. An evolutionary approach for Pareto-optimal configurations in SOC platforms. In Kluwer Academic Pulishers, editor, SOC Design Methodologies, 2002.
  6. G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In Kluwer Academic Publishers, editor, System on Chip for Realtime Systems, 2002.

Conferences

  1. P. Puigdemont, E. Russo, A. Wassington, A. Das, S. Abadal, M. Palesi, “A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference”, 30th Asia and South Pacific Design Automation Conference (ASP-DAC 2025), Jan 20-23, 2025, Tokyo, Japan.
  2. Hamaad Rafique, Davide Patti, Maurizio Palesi and Gaetano Carmelo La Delfa, “Fusing Visuals with Magnetic Signals to Improve Indoor Localization Using Vision Transformers”, 14th International Conference on Indoor Positioning & Indoor Navigation (IPIN2024), October 14-17, 2024, Hong Kong.
  3. Elio Vinciguerra, Enrico Russo, Maurizio Palesi and Giuseppe Ascia, “Data-Driven Simulation Based Fault Detection in Automotive RISC-V Applications”, 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024), December 16-19, 2024, Kuala Lumpur, Malaysia.
  4. Maurizio Palesi, Enrico Russo, Davide Patti, Giuseppe Ascia and Vincenzo Catania, “Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures”, 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024), December 16-19, 2024, Kuala Lumpur, Malaysia.
  5. Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania, “Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems”, IEEE International Symposium on Circuits and Systems (ISCAS), May 19-22. 2024, Singapore.
  6. Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia and Vincenzo Catania, “A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning”, Design Automation Conference (DAC), June 23-27, 2024, San Francisco, USA.
  7. Marco Finocchiaro, Salvatore Monteleone, Enrico Russo, Maurizio Palesi and Davide Patti, “Lessons Learned on the Design of Cost-Effective and Highly Compatible Smart Gloves”, 13th Mediterranean Conference on Embedded Computing (MECO), June 11-14, 2024, Budva, Montenegro.
  8. Hamaad Rafique, Davide Patti, Maurizio Palesi, Gaetano Carmelo La Delfa, Vincenzo Catania, “Optimization Technique for Indoor Localization: A Multi-Objective Approach to Sampling Time and Error Rate Trade-off”, IEEE International Conference on Signal, Control and Communication, 1-3 December 2023, Tunisia.
  9. Grazia Veronica Aiosa, Maurizio Palesi, Francesca Sapuppo, Maria Gabriella Xibilia, “Explainable AI-based Clinical Decision Support System for Obesity Comorbidity Analysis”, IEEE International Workshop on Artificial Intelligence for Health, 9-13 October, 2023 - Limassol, Cyprus.
  10. M. Palesi, E. Russo, A. Das and J. Jose, Wireless Enabled Inter-Chiplet Communication in DNN Hardware Accelerators, IEEE International Parallel & Distributed Processing Symposium, Workshop on AI for Datacenter Operations, May 15-19, 2023.
  11. H. Rafique, D. Patti, M. Palesi, V. Catania, m-BMC: Exploration of Magnetic Field Measurements for Indoor Positioning Using mini-Batch Magnetometer Calibration, IEEE International Conference on Mobility: Operations, Services, and Technologies (MOST), 2023
  12. Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Ascia, G.; Catania, V.. MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022), DOI: 10.23919/DATE54114.2022.9774747
  13. E. Russo, M. Palesi, D. Patti, H. Lahdhiri, S. Monteleone, G. Ascia, V. Catania:, "Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators," 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lyon, France, 2022, pp. 16-23, doi: 10.1109/IPDPSW55747.2022.00013.
  14. Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Habiba Lahdhiri, Giuseppe Ascia, Vincenzo Catania: Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators, 2022 11th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, 2022, pp. 1-4, doi: 10.1109/MECO55406.2022.9797095.
  15. G. Canzonieri, S. Monteleone, M. Palesi, E. Russo, and D. Patti. 2022. Analyzing the Impact of DNN Hardware Accelerators-Oriented Compression Techniques on General-Purpose Low-End Boards. In Mobile Web and Intelligent Information Systems: 18th International Conference, MobiWIS 2022, Rome, Italy, August 22–24, 2022, Proceedings. Springer-Verlag, Berlin, Heidelberg, 143–155. https://doi.org/10.1007/978-3-031-14391-5_11
  16. Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Ascia, G.; Catania, V.. LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. IEEE Annual Conference on Pervasive Computing and Communications Workshops (PerCom), DOI: 10.1109/PerComWorkshops51409.2021.9431078, 2021.
  17. Zhi, Hc; Xu, Xn; Han, Wj; Gao, Zl; Wang, Xh; Palesi, M; Singh, Ak; Huang, Lt. A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators. NANOCOM '21: Proceedings of the Eight Annual ACM International Conference on Nanoscale Computing and Communication, DOI: 10.1145/3477206.3477459
  18. Ascia, G.; Catania, V.; Mineo, A.; Monteleone, S.; Palesi, M.; Patti, D.. Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. 14th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2020, DOI: 10.1109/NOCS50636.2020.9241714
  19. Ascia, G.; Catania, V.; Jose, J.; Monteleone, S.; Palesi, M.; Patti, D.. Improving inference latency and energy of network-on-chip based convolutional neural networks through weights compression. Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020, DOI: 10.1109/IPDPSW50202.2020.00017
  20. Mnejja, S.; Aydi, Y.; Abid, M.; Monteleone, S.; Palesi, M.; Patti, D.. Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs. Advances in Intelligent Systems and Computing, DOI: 10.1007/978-3-030-44041-1_48, 2020.
  21. Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J.. Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. 2019 6th International Conference on Internet of Things: Systems, Management and Security, IOTSMS 2019, DOI: 10.1109/IOTSMS48152.2019.8939236
  22. Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J.. Analyzing networks-on-chip based deep neural networks. Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2019, DOI: 10.1145/3313231.3352375
  23. Xiao, S.; Wang, X.; Palesi, M.; Singh, A. K.; Mak, T.. ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, DOI: 10.23919/DATE.2019.8715189
  24. Ascia, Giuseppe; Catania, Vincenzo; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide; Jose, John. Approximate Wireless Networks-on-Chip. Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018, DOI: 10.1109/DCIS.2018.8681491
  25. Deb, D.; Jose, J.; Palesi, M.. Performance enhancement of caches in TCMPs using near vicinity prefetcher. Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019, DOI: 10.1109/VLSID.2019.0002
  26. Biondi, S.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.. smARTWorks: A multi-sided context-aware platform for the smart museum. Proceedings of the 8th International Joint Conference on Pervasive and Embedded Computing and Communication Systems, PECCS 2018, DOI: 10.5220/0006907302410247
  27. Sleeba, S. Z.; Jose, J.; Palesi, M.; James, R. K.; Mini, M. G.. Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, DOI: 10.1109/VLSI-SoC.2018.8645011, 2018
  28. Das, Abhijit; Babu, Sarath; Jose, John; Jose, Sangeetha; Palesi, Maurizio. Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, DOI: 10.1109/NOCS.2018.8512164
  29. Ascia, Giuseppe; Catania, Vincenzo; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide; Jose, John. Improving energy consumption of NoC based architectures through approximate communication. 2018 7th Mediterranean Conference on Embedded Computing, MECO 2018 - Including ECYPS 2018, Proceedings, DOI: 10.1109/MECO.2018.8406045
  30. Catania, Vincenzo; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide. Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation. ISC High Performance 2018, DOI: 10.1007/978-3-319-92040-5_16
  31. Shahrizal Rusli, Mohd; Lit, Asrani; Nadzir Marsono, Muhammad; Palesi, Maurizio. Adaptive Packet Relocator in Wireless Network-on-Chip (WiNoC). Modeling, Design and Simulation of Systems, DOI: 10.1007/978-981-10-6502-6_61, 2017
  32. Patti, Davide; Ebrahimi, Masoumeh; Hollstein, Thomas; Daneshtalab, Masoud; Palesi, Maurizio; Wang, Xiaohang. Message from the Chairs [NoCArc 2017]. NoCArc'17: Proceedings of the 10th International Workshop on Network on Chip Architectures, DOI:
  33. Moreac, Erwan; Laurent, Johann; Bomel, Pierre; Rossi, Andre; Boutillon, Emmanuel; Palesi, Maurizio. Energy aware Networks-on-Chip cortex inspired communication. 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), DOI: 10.1109/PATMOS.2017.8106952
  34. Palesi, Maurizio; Daneshtalab, Masoud; Wang, Xiaohang; Ebrahimi, Masoumeh; Patti, Davide. Message from the chairs [NoCArc 2016]. NoCArc'16: Proceedings of the 9th International Workshop on Network on Chip Architectures.
  35. Monemi, Alireza; Ooi Chia, Yee; Marsono Muhammad, Nadzir; Palesi, Maurizio. Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. NoCArc'16: Proceedings of the 9th International Workshop on Network on Chip Architectures, DOI: 10.1145/2994133.2994134
  36. Rezaei, Amin; Daneshtalab, Masoud; Palesi, Maurizio; Zhao, Danella. Efficient Congestion-Aware Scheme for Wireless on-Chip Networks. 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), DOI: 10.1109/PDP.2016.88
  37. Catania, Vincenzo; Mineo, A.; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide. Energy efficient transceiver in wireless Network on Chip architectures. Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, DOI: 10.3850/9783981537079_0736
  38. Catania, Vincenzo; Mineo, A; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide. Improving the energy efficiency of wireless Network on Chip architectures through online selective buffers and receivers shutdown. 2016 13th IEEE Annual Consumer Communications & Networking Conference (CCNC), DOI: 10.1109/CCNC.2016.7444860
  39. MOHD SHAHRIZAL, R; OOI CHIA, Y; Marsono, M; Yaghini, P; Bagherzadeh, N; Patti, Davide; Catania, Vincenzo; Palesi, Maurizio. An Energy Aware Transmission Control in Wireless Network-on-Chip. Proceedings of the 14th International Conference on Applied Computer and Applied Computational Science (ACACOS '15).
  40. Catania, Vincenzo; Mineo, A; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide. Noxim: An open, extensible and cycle-accurate network on chip simulator. Proceedings of the ASAP2015 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors, DOI: 10.1109/ASAP.2015.7245728
  41. Mineo, A; Rusli M., S; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.. A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. Proceeding of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), DOI: 10.7873/date.2015.0664
  42. Fattah, M.; Palesi, Maurizio; Liljeberg, P.; Tenhunen, H.. SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. Design Automation Conference, 2014, pp. 1-6, doi: 10.1145/2593069.2593214.
  43. X. Wang, X.; Zhao, B.; Mak, T.; Yang, M.; Jiang, Y.; Daneshtalab, M.; Palesi, Maurizio. Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model. Design Automation and Test in Europe (DATE 2014).
  44. Rusli, M. S.; Mineo, A.; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.. A closed loop control based power manager for WiNoC architectures. ACM International Conference Proceeding Series, DOI: 10.1145/2613908.2613914, 2014.
  45. Sgro, F.; Monteleone, G.; Palesi, Maurizio; Lipoma, M.. An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor. Atti del IV Congresso nazionale di Bioingegneria.
  46. Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo. An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs. 17th Design, Automation and Test in Europe, DATE 2014; Dresden; Germany; 24 March 2014 through 28 March 2014, DOI: 10.7873/DATE2014.284
  47. Ascia, Giuseppe; Palesi, Maurizio; Catania, Vincenzo. An adaptive output selection function based on a fuzzy rule base system for Network on Chip. Proc of EUROMICRO DSD/SEAA 2013, DOI: 10.1109/DSD.2013.60
  48. Masi, M; Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo. Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. Proc. of 11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2013), DOI: 10.1109/HPCC.and.EUC.2013.300
  49. Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo. NoC Links Energy Reduction through Link Voltage Scaling. Proc. of 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013, DOI: 10.1109/SAMOS.2013.6621113
  50. Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo. Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. EUROMICRO DSD/SEAA 2013, DOI: 10.1109/DSD.2013.106
  51. M., Ebrahimi; M., Daneshtalab; F., Farahnakian; P., Liljeberg; J., Plosila; Palesi, Maurizio; H., Tenhunen. HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks. 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 2012.
  52. D., Salemi; Palesi, Maurizio; Catania, Vincenzo. Power-Aware Selection Policy for Networks on Chip. 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'11), DOI: 10.1109/DTIS.2011.5941422
  53. Patti, Davide; Spadaccini, A; Palesi, Maurizio; Fazzino, F; Catania, Vincenzo. Improving the Teaching Effectiveness in an Introductory Computer Architecture Course. International Conference on Computational Intelligence and Software Engineering.
  54. X., Wang; Palesi, Maurizio; M., Yang; Y., Jiang; M. C., Huang; P., Liu. Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. Lecture Notes in Computer Science, Network and Parallel Computing Conference, 2011.
  55. Al, Dujaily; T., Mak; F., Xia; A., Yakovlev; Palesi, Maurizio. Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks. Design Automation and Test in Europe (DATE 2011). 14-18 March 2011, Grenoble, France.
  56. X., Wang; Palesi, Maurizio; M., Yang; Y., Jiang; M. C., Huang; P., Liu. Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs. VLSI System on Chip. October 2011, Kowloon, Hong Kong, China.
  57. Palesi, Maurizio; Holsmark, R; Wang, X; Kumar, S; Yang, M; Jiang, Y; Catania, Vincenzo. An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip. 4th Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, 2010.
  58. R., Holsmark; S., Kumar; Palesi, Maurizio. A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms. 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), August 31, 2010, Ischia - Naples, Italy.
  59. Palesi, Maurizio; R., Holsmark; X., Wang; S., Kumar; M., Yang; Y., Jiang; Catania, Vincenzo. An efficient technique for in-order packet delivery with adaptive routing algorithms in networks on chip. 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, 2010, DOI: 10.1109/DSD.2010.53
  60. Ascia, Giuseppe; Catania, Vincenzo; Fazzino, F; Palesi, Maurizio. An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip. IEEE International Conference on Computer Engineering and Systems, IEEE International Conference on Computer Engineering and Systems 2009, DOI: 10.1109/ICCES.2009.5383319
  61. Palesi, Maurizio; Fazzino, F; Ascia, Giuseppe; Catania, Vincenzo. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. 12th Euromicro Conference on Digital System Design, 2009, DOI: 10.1109/DSD.2009.203
  62. Holsmark, R; Palesi, Maurizio; Kumar, S; Mejia, A.. HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip. 3rd ACM/IEEE International Symposium on Networks on Chip, 2009.
  63. Catania, Vincenzo; DE FRANCISCI MORALES, G; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures. 12th Euromicro Conference on Digital System Design, 2009.
  64. Palesi, Maurizio; Kumar, S.. Message from the Chairs [NoCArc 2009]. NoCArc'09: Proceedings of the 2nd International Workshop on Network on Chip Architectures.
  65. Tornero, R; Sterrantino, V; Palesi, Maurizio; Orduna, J. M.. A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip. IEEE/ACM International Symposium on Parallel & Distributed Processing, 2009.
  66. DI NUOVO, A.; GIANMARCO DE FRANCISCI, Morales; Palesi, Maurizio; Patti, Davide. System Level Design of Application Domain-specific Embedded System Architectures.. ACACES 2009 Poster Abstracts.
  67. Frazzetta, D; Dimartino, G; Palesi, Maurizio; Kumar, S; Catania, Vincenzo. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, 2008.
  68. Catania, Vincenzo; DE FRANCISCI MORALES, Gianmarco; DI NUOVO, A. G.; Palesi, Maurizio; Patti, Davide. High Performance Computing for Embedded System Design: A Case Study. Proceedings of 11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools, 2008.
  69. Longo, G; Signorino, S; Palesi, Maurizio; Kumar, S; Holsmark, R; Catania, Vincenzo. Bandwidth Aware Routing Algorithms for Networks-on-Chip. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip.
  70. Tornero, R; ORDUNA J., M; Palesi, Maurizio; Duato, J.. A Communication-Aware Topological Mapping Technique for NoCs. 14th International Conference on Parallel and Distributed Computing, 2008.
  71. Palesi, Maurizio; Longo, G; Signorino, S; Kumar, S; Holsmark, R; Catania, Vincenzo. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, 2008.
  72. Palesi, Maurizio; Kumar, S; Holsmark, R; Catania, Vincenzo. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IEEE International Parallel and Distributed Processing Symposium, 2007.
  73. DI NUOVO A., G; Palesi, Maurizio; Catania, Vincenzo. Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. Proceedings of 2007 IEEE International Conference on Fuzzy Systems (FUZZIEEE '07), DOI: 10.1109/FUZZY.2007.4295660
  74. Ascia, Giuseppe; Catania, Vincenzo; A., DI NUOVO; Palesi, Maurizio; Patti, Davide. Fuzzy Simulation to Speedup Computer Design. Proceedings of 4th Industrial Simulation Conference (ISC 2006).
  75. DI NUOVO, A.; Catania, Vincenzo; Palesi, Maurizio. The Hybrid Genetic Fuzzy C-Means: a Reasoned Implementation. Proceedings of 7th WSEAS International Conference on Fuzzy Systems (FS '06),
  76. Giuseppe, Ascia; Vincenzo, Catania; DI NUOVO, A. G.; Palesi, Maurizio; Patti, Davide. An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006).
  77. Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, Vincenzo. A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems. Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, 2007.
  78. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. Embedded Systems for Real Time Multimedia, Proceedings of the 2006 IEEE/ACM/IFIP Workshop on, DOI: 10.1109/ESTMED.2006.321278
  79. Holsmark, R; Palesi, Maurizio; Kumar, S.. Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006, 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools.
  80. Ascia, Giuseppe; Catania, Vincenzo; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide. A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. Proceedings of 2006 IEEE Conference on Evolutionary Computation, DOI: 10.1109/CEC.2006.1688287
  81. Palesi, Maurizio; Kumar, S; Holsmark, R.. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, 2006.
  82. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. A New Selection Policy for Adaptive Routing in Network on Chip. Proc. of 5th WSEAS International Conference on ELECTRONICS, HARDWARE, WIRELESS and OPTICAL COMMUNICATIONS.
  83. DI NUOVO A., G; Palesi, Maurizio; Patti, Davide; Ascia, Giuseppe; Catania, Vincenzo. Fuzzy Decision Making in Embedded System Design. Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, 2006, DOI: 10.1145/1176254.1176309
  84. DI NUOVO, A.; Palesi, Maurizio; Patti, Davide. An Hybrid Soft Computing Approach for Automated Computer Design. STAIRS 2006 - Proceedings of the Third Starting AI Researchers' Symposium.
  85. Ascia, Giuseppe; Catania, Vincenzo; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide. An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design. Proceedings of Embedded Computer Systems: Architectures, MOdeling, and Simulation 2006, DOI: 10.1109/ICSAMOS.2006.300817
  86. Ascia, G; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Power/Energy Perspective on Hyperblock Formation. International Conference on High Performance Computing, 2004.
  87. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. An Evolutionary Approach to Network on Chip Mapping Problem. Evolutionary Computation, 2005. The 2005 IEEE Congress on, DOI: 10.1109/CEC.2005.1554674
  88. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. Proceedings of the 2005 conference on Asia South Pacific design automation, DOI: 10.1109/ASPDAC.2005.1466494
  89. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Exploring Design Space of VLIW Architectures. Proc. of IEEE 16th International Conference on Application-specific Systems, Architectures and Processors, 2005, DOI: 10.1109/ASAP.2005.33
  90. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures. Proc. of IEEE International Symposium on Circuits and Systems 2005, DOI: 10.1109/ISCAS.2005.1465530
  91. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Multi-Objective Optimization of a Prameterized VLIW Architecture. NASA/DoD Conference on Evolvable Hardware, 2004, DOI: 10.1109/EH.2004.1310830
  92. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. Multi-objective mapping for mesh-based NoC architectures. Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2004, DOI: 10.1109/CODESS.2004.241215
  93. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. Power/Energy Perspective on Hyperblock Formation. Proceedings of the international Conference on High Performance Computing 2004.
  94. G., Ascia; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia).
  95. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide. EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration. First Workshop on Embedded Systems for Real-Time Multimedia.
  96. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. Proc. of PATMOS 2003.
  97. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A.. An evolutionary approach for reducing the switching activity in address buses. Proceedings of IEEE Congress on Evolutionary Computation, 2003, DOI: 10.1109/CEC.2003.1299563
  98. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A.. A genetic approach to bus encoding. Proceedings of International Conference on Very Large Scale Integration of System-on-Chip, 2003.
  99. Palesi, Maurizio; Givargis, T.. Multi-objective design space exploration using genetic algorithms. Tenth International Symposium on Hardware/Software Codesign, 2002.
  100. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. Tuning methodologies for parameterized systems design. Proceedings of IEEE International workshop on system-on-Chip for Real-Time Applications, 2003.
  101. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. A Framework for Design Space Exploration of Parameterized VLSI Systems. Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, DOI: 10.1109/ASPDAC.2002.994930
  102. Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio. Design Space Exploration Methodologies for IP-based System-on-a-chip. Proc. of ISCAS 2002, DOI: 10.1109/ISCAS.2002.1011000
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