In the Smart Grid, a reliable communication platform is needed for conveying huge amount of data ... more In the Smart Grid, a reliable communication platform is needed for conveying huge amount of data among S mart Grid's communication subsystems. Thus, the design of the reliable communication platform is of key importance for data availability and better decisions. In this article, the major challenges to Transmission Control Protocol/Internet Protocol (TCP/IP) are identified, and addressed. The TCP/IP protocol stack is implemented as software, and as hardware on an FPGA. In the hardware implementation, a MAC layer from Altera defined as Triple-speed Ethernet (TS E) is configured and synthesized. We verified the designs via transmitting TCP/IP packets to both a Logic Analyzer and a Network Protocol Analyzer. Finally, we integrated Elliptic Curve Cryptography (ECC) with both hardware and software implementation on an FPGA. We discuss the importance of ECC, its advantages and disadvantages, and the challenge of mapping a message into a point on the curve and the architecture of our ...
ABSTRACT Elliptic Curve Cryptography (ECC) over a Galois Field GF(2m) offers a high security leve... more ABSTRACT Elliptic Curve Cryptography (ECC) over a Galois Field GF(2m) offers a high security level relative to other protocols (i.e., RSA) but with smaller keys' sizes. In this paper, we consider the finite field multiplication and addition used in elliptic curve cryptography to design sequential, and then, concurrent reconfigurable ecrypto system to encrypt and decrypt a message. FPGA implementation via VHDL language has been completed to analyze the time and area required in both scenarios. Our approach, and for the first time, consider mapping a message on the elliptic curve concurrently.
Embedded system cores for communications networks are becoming much important recently due to the... more Embedded system cores for communications networks are becoming much important recently due to the demands placed by Smart Grid, sensor mobile networks, etc. However, embedded system designs have unique metrics such as cost, flexibility, and size. Tuning these metrics during embedded system designs will definitely impact the cost and performance of Smart Grid devices and systems. In this research, we
ABSTRACT In this research, we develop a high-performance reliable communication platform. The pla... more ABSTRACT In this research, we develop a high-performance reliable communication platform. The platform consists of two parts, TCP/IP protocol stack that is implemented as hardware on an FPGA. And the second part is an integrated Triple-speed Ethernet (TSE). We designed a state machine that configures TSE and an Ethernet frame generator to send TCP/IP packets at 1 Gbps, which are then driven into Logic Analyzer for a design synthesis and verification process.
Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST), 2012
Embedded system cores for communications networks are becoming much important recently due to the... more Embedded system cores for communications networks are becoming much important recently due to the demands placed by Smart Grid, sensor mobile networks, etc. However, embedded system designs have unique metrics such as cost, flexibility, and size. Tuning these metrics during embedded system designs will definitely impact the cost and performance of Smart Grid devices and systems. In this research, we
In the Smart Grid, a reliable communication platform is needed for conveying huge amount of data ... more In the Smart Grid, a reliable communication platform is needed for conveying huge amount of data among S mart Grid's communication subsystems. Thus, the design of the reliable communication platform is of key importance for data availability and better decisions. In this article, the major challenges to Transmission Control Protocol/Internet Protocol (TCP/IP) are identified, and addressed. The TCP/IP protocol stack is implemented as software, and as hardware on an FPGA. In the hardware implementation, a MAC layer from Altera defined as Triple-speed Ethernet (TS E) is configured and synthesized. We verified the designs via transmitting TCP/IP packets to both a Logic Analyzer and a Network Protocol Analyzer. Finally, we integrated Elliptic Curve Cryptography (ECC) with both hardware and software implementation on an FPGA. We discuss the importance of ECC, its advantages and disadvantages, and the challenge of mapping a message into a point on the curve and the architecture of our ...
ABSTRACT Elliptic Curve Cryptography (ECC) over a Galois Field GF(2m) offers a high security leve... more ABSTRACT Elliptic Curve Cryptography (ECC) over a Galois Field GF(2m) offers a high security level relative to other protocols (i.e., RSA) but with smaller keys' sizes. In this paper, we consider the finite field multiplication and addition used in elliptic curve cryptography to design sequential, and then, concurrent reconfigurable ecrypto system to encrypt and decrypt a message. FPGA implementation via VHDL language has been completed to analyze the time and area required in both scenarios. Our approach, and for the first time, consider mapping a message on the elliptic curve concurrently.
Embedded system cores for communications networks are becoming much important recently due to the... more Embedded system cores for communications networks are becoming much important recently due to the demands placed by Smart Grid, sensor mobile networks, etc. However, embedded system designs have unique metrics such as cost, flexibility, and size. Tuning these metrics during embedded system designs will definitely impact the cost and performance of Smart Grid devices and systems. In this research, we
ABSTRACT In this research, we develop a high-performance reliable communication platform. The pla... more ABSTRACT In this research, we develop a high-performance reliable communication platform. The platform consists of two parts, TCP/IP protocol stack that is implemented as hardware on an FPGA. And the second part is an integrated Triple-speed Ethernet (TSE). We designed a state machine that configures TSE and an Ethernet frame generator to send TCP/IP packets at 1 Gbps, which are then driven into Logic Analyzer for a design synthesis and verification process.
Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST), 2012
Embedded system cores for communications networks are becoming much important recently due to the... more Embedded system cores for communications networks are becoming much important recently due to the demands placed by Smart Grid, sensor mobile networks, etc. However, embedded system designs have unique metrics such as cost, flexibility, and size. Tuning these metrics during embedded system designs will definitely impact the cost and performance of Smart Grid devices and systems. In this research, we
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Papers by Rami Amiri