Supported by the National Science Foundation (NSF grant #CCR9971168), Professor Myers and his colleagues demonstrated the viability of analog architectures for MAP decoders. This project led to the design of the first successful analog MAP decoder using strictly CMOS design. The fabricated chip was tested at bit rates of 1 Mb/s to 10 Mb/s with a typical power consumption of only 16uW.  Under NSF CCF award 1117515, Professor Myers in collaboration with Professor Peng Li of Texas A&M integrated research in the area of analog circuit verification with analog testing, and applying this work to the challenges of modern analog circuit designs that include extensive digital components. During this project, we continued to develop our LEMA verification tool including improvements to our model generation tool, a new verification property language for analog/mixed-signal circuits, and new verification methods.  This work built upon past projects supported by the Semiconductor Research Corporation and additional support from Intel Corporation.

Faculty:

• Chris J. Myers, Professor, University of Utah
• Peng Li, Professor, Texas A&M University
• Chris Winstead, Associate Professor, Utah State University
• Tomohiro Yoneda, Professor, National Institute of Informatics

Alumni:

• Satish Batchu (MS), Qualcomm, Raleigh, NC.
• Jie Dai (PhD), Director of IP Dept. in Brite Semiconductor (Shanghai) Corporation.
• Andrew Fisher (PhD), Sandia National Laboratories, Albuquerque, NM.
• Kevin Jones (BS), Aberdeen Proving Ground, Philadelphia, PA.
• Dhanashree Kulkarni (MS), Intel Corporation, Hillsboro, OR.
• Scott Little (PhD), Freescale, Austin, TX.
• Nick Seegmiller (BS), Backcountry.com, Park City, UT.
• Robert Thacker (PhD), IBM Austin, TX.
• David Walter (PhD), Associate Professor, Virginia State University, Petersburg, VA.
• Hao Zheng (PhD), Associate Professor, University of South Florida.

Software:

• LEMA

PhD Dissertations:

• Andrew N. Fisher, Efficient, Sound Formal Verification for Analog/Mixed-Signal Circuits , PhD Dissertation, University of Utah, August, 2015.
• Scott Little, Efficient Modeling and Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets , PhD Dissertation, University of Utah, December, 2008.
• David C. Walter, Verification of Analog and Mixed-Signal Circuits Using Symbolic Methods , PhD Dissertation, University of Utah, August, 2007.

Master’s Theses:

• Dhanashree Kulkarni, Improved model generation and property specification for analog/mixed-signal circuits , MS Thesis, University of Utah, August, 2013.
• Satish Batchu, Automatic Extraction of Behavioral Models from Simulations of Analog/Mixed-Signal (AMS) Circuits , MS Thesis, University of Utah, December, 2010.

Bachelor’s Theses:

• S. Little, A Comparison of Timed State Space Analysis Methods, BS Thesis, University of Utah, June, 2003.

Book Chapters:

• A. Fisher, D. Kulkarni, and C. Myers, A new assertion property language for analog/mixed-signal circuits, in Languages, Design Methods, and Tools for Electronic System Design – Selected Contributions from FDL 2013, Lecture Notes in Electrical Engineering, Volume 311, pages 45- 65, 2015.

Journal Publications:

• X. Li, C. Myers, and C. Kashyap, Guest Editors’ Introduction Challenges and Opportunities in Analog/Mixed-Signal CAD, in IEEE Design & Test, 33(5): 5-6, 2016.
• V. Dubikhin, D. Sokolov, C. Myers, and A. Yakovlev, Design of Mixed-signal Systems with Asynchronous Control, in IEEE Design and Test Magazine, 33(5): 44-55, 2016.
• S.Little, D.Walter, C.Myers, R.Thacker, S.Batchu, and T.Yoneda, Verification of analog/mixed-signal circuits using labeled hybrid Petri nets, in IEEE Transactions on CAD, 30(4): 617-630, April, 2011.
• S. Little, D. Walter, K. Jones, C. Myers, and A. Sen, Analog/mixed-signal circuit verification using models generated from simulation traces, in The International Journal of Foundations of Computer Science, 21(2): 191-210, 2010.
• D. Walter, S. Little, C. Myers, N. Seegmiller, and T. Yoneda, Verification of analog/mixed-signal circuits using symbolic methods, in IEEE Transactions on CAD, 27(12): 2223-2235, December, 2008.
• C. Myers, R. Harrison, D. Walter, N. Seegmiller, and S. Little, The case for analog circuit verification , in Electronic Notes in Theoretical Computer Science, 153(3): 53-63, June 20, 2006.
• C. Winstead, J. Dai, S. Yu, C. Myers, R. Harrison, C. Schlegel, CMOS analog MAP decoder for (8,4) Hamming Code, in Journal of Solid State Circuits, 39(1), 122-131, January, 2004.

Conference and Workshop Papers:

• V. Dubikhin, D. Sokolov, C. Myers, A. Mokhov, and, A. Yakovlev, Model discovery for analog/mixed-signal circuits, in 2017 Frontiers in Analog CAD Workshop, July, 2017.
• V. Dubikhin, C. Myers, D. Sokolov, I. Syranidis, and, A. Yakovlev, INVITED: Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems, in 2017 Design Automation Conference, June, 2017.
• A. Fisher, C. Myers, and P. Li, Reachability analysis using extremal rates, in 7th Nasa Formal Methods Symposium, April, 2015.

• A. Fisher, S. Batchu, K. Jones, D. Kulkarni, S. Little, D. Walter, and C. Myers, LEMA: a tool for the formal verification of digitally-intensive analog/mixed-signal circuits, in 2014 Midwest Symposium on Circuits and Systems, August, 2014.
• D. Kulkarni, A. Fisher, and C. Myers, A new assertion property language for analog/mixed- signal circuits, in 2013 Forum on Design Languages, September, 2013 (best paper candidate).
• H. Lin, P. Li, and C. Myers, Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis, to appear in 2013 Design Automation Conference, June, 2013.
• D. Kulkarni, S. Batchu, and C. Myers, Improved model generation of AMS circuits for formal verification, in 2011 Virtual Worldwide Forum for PhD Researchers in Electronic Design Automation, November, 2011.
• S. Little and C. Myers, Abstract modeling and simulation aided verification of analog/mixed-signal cirucits, in The Workshop on Formal Verification of Analog Circuits, July, 2008.
• S. Little, A. Sen, and C. Myers, Application of automated model generation techniques to analog/mixed-signal circuits, in 8th International Workshop on Microprocessor Test and Verification, December, 2007.
• S. Little, D. Walter, K. Jones, and C. Myers, Analog/mixed-signal circuit verification using models generated from simulation traces, in Automated Technology for Verification and Analysis, October, 2007.
• D. Walter, S. Little, and C. Myers, Bounded model checking of analog and mixed-signal circuits using an SMT solver, in Automated Technology for Verification and Analysis, October, 2007.
• D. Walter, S. Little, N. Seegmiller, C. Myers, and T. Yoneda, Symbolic model checking of analog/mixed-signal circuits, in 2007 Asia and South Pacific Design Automation Conference, January, 2007.
• S. Little, N. Seegmiller, D. Walter, C. Myers, and T. Yoneda, Verification of analog/mixed-signal circuits using labeled hybrid Petri nets, in 2006 International Conference on Computer-Aided Design, November, 2006.
• C. Myers, R. Harrison, D. Walter, N. Seegmiller, and S. Little, The case for analog circuit verification , in The Workshop on Formal Verification of Analog Circuits, April, 2005.
• S. Little, D. Walter, N. Seegmiller, C. Myers, and T. Yoneda, Verification of analog and mixed-signal circuits using timed hybrid Petri nets, in Automated Technology for Verification and Analysis, November, 2004.
• C. Winstead, J. Dai, S. Yu, R. Harrison, C. Myers, and C. Schlegel, Analog decoding of product codes, in International Symposium on Information Theory, June, 2002.
• J. Dai, C. J. Winstead, C. J. Myers, R. R. Harrison, and C. Schlegel, Cell library for automatic synthesis of analog error control decoders, in Proc. International Symposium on Circuits and Systems(ISCAS), pages 481-484, May, 2002.
• C. Winstead, C. Myers, C. Schlegel, and R. Harrison, Analog decoding of product codes, in 2001 IEEE Information Theory Workshop, pages 131-133, September, 2001.
• C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, and C. Schlegel Analog MAP Decoder for (8,4) Hamming code in subthreshold CMOS, in International Symposium on Information Theory, June, 2001.
• C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, and C. Schlegel Analog MAP Decoder for (8,4) Hamming code in subthreshold CMOS, in 2001 Advanced Research in VLSI Conference, pages 132-147, March, 2001.