Abstract Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities... more Abstract Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. A testable design approach is presented for on-line detection of certain error conditions ...
International Symposium on Microarchitecture, Nov 30, 1990
Abstract A testing procedure is given for a microprogrammed processor. The conventional procedure... more Abstract A testing procedure is given for a microprogrammed processor. The conventional procedure to generate test vectors is used instead of C-testability for the bit-slice microprocessor. The minimal complete test sequences are calculated for the micro-sequencer and the ALU, and stored in the micro-memory. Micro-memory is implemented by an electrically erasable PLA which has the capability to test itself using a universal test set. A one-bit wide processor section is assumed. However, the method can be extended to a ...
Now welcome, the most inspiring book today from a very professional writer in the world, software... more Now welcome, the most inspiring book today from a very professional writer in the world, software reliability models developments evaluation and applications. This is the book that many people in the world waiting for to publish. After the announced of this book, the book lovers are really curious to see how this book is actually. Are you one of them? That's very proper. You may not be regret now to seek for this book to read.
Introduction: For MOS devices it is now recognised that the gate level models do not represent so... more Introduction: For MOS devices it is now recognised that the gate level models do not represent some failure modes.1"3 It is therefore necessary to consider test generation at the transistor level. Test generation algorithms have been developed which use two types of transistor level description of the circuit. The first type of algorithm uses a model called a grid or characteristic graph description of a gate. The second type of algorithm uses a model called the basic cell matrix (BCM) description of each gate. Here each gate is considered as a matrix of n rows and m ...
Abstract Effects of built-in current sensors on I DDQ measurement as well as on the performance o... more Abstract Effects of built-in current sensors on I DDQ measurement as well as on the performance of the circuit under test are considered. Most of the Built-in Current Sensor designs transform the ground terminal of the circuit under test to a virtual ground. This causes increase in both propagation delay as well as I DDQ sampling time with increase in the number of gates, affecting both test as well as operational performance. The effect that the current sensor has on the operational and test performance is considered. Circuit ...
Abstract Software reliability engineering must develop beyond statistical analysis of data and an... more Abstract Software reliability engineering must develop beyond statistical analysis of data and analytic models which frequently require unrealistic assumptions. We must develop a viable discipline of simulation to aid experimental and industrial application of software reliability engineering. This will require developing standard modeling components, connections, tools, and a body of knowledge to interpret the phenomena that are being modeled. This paper explains how and why simulation models of software reliability can ...
Abstract With the advent of VLSI (Very Large Scale Integration), the importance of CMOS (Compleme... more Abstract With the advent of VLSI (Very Large Scale Integration), the importance of CMOS (Complementary Metal Oxide Semiconductor) technology has increased. CMOS offers some very significant advantages over NMOS, and has emerged very competitive. Therefore, testability of CMOS devices is of considerable importance. CMOS devices exhibit some failure modes which are not adequately represented by the classical stuck-at fault model. A new fault model is introduced here to represent such faults. Leakage faults are specifically ...
Abstract Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities... more Abstract Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. A testable design approach is presented for on-line detection of certain error conditions ...
International Symposium on Microarchitecture, Nov 30, 1990
Abstract A testing procedure is given for a microprogrammed processor. The conventional procedure... more Abstract A testing procedure is given for a microprogrammed processor. The conventional procedure to generate test vectors is used instead of C-testability for the bit-slice microprocessor. The minimal complete test sequences are calculated for the micro-sequencer and the ALU, and stored in the micro-memory. Micro-memory is implemented by an electrically erasable PLA which has the capability to test itself using a universal test set. A one-bit wide processor section is assumed. However, the method can be extended to a ...
Now welcome, the most inspiring book today from a very professional writer in the world, software... more Now welcome, the most inspiring book today from a very professional writer in the world, software reliability models developments evaluation and applications. This is the book that many people in the world waiting for to publish. After the announced of this book, the book lovers are really curious to see how this book is actually. Are you one of them? That's very proper. You may not be regret now to seek for this book to read.
Introduction: For MOS devices it is now recognised that the gate level models do not represent so... more Introduction: For MOS devices it is now recognised that the gate level models do not represent some failure modes.1"3 It is therefore necessary to consider test generation at the transistor level. Test generation algorithms have been developed which use two types of transistor level description of the circuit. The first type of algorithm uses a model called a grid or characteristic graph description of a gate. The second type of algorithm uses a model called the basic cell matrix (BCM) description of each gate. Here each gate is considered as a matrix of n rows and m ...
Abstract Effects of built-in current sensors on I DDQ measurement as well as on the performance o... more Abstract Effects of built-in current sensors on I DDQ measurement as well as on the performance of the circuit under test are considered. Most of the Built-in Current Sensor designs transform the ground terminal of the circuit under test to a virtual ground. This causes increase in both propagation delay as well as I DDQ sampling time with increase in the number of gates, affecting both test as well as operational performance. The effect that the current sensor has on the operational and test performance is considered. Circuit ...
Abstract Software reliability engineering must develop beyond statistical analysis of data and an... more Abstract Software reliability engineering must develop beyond statistical analysis of data and analytic models which frequently require unrealistic assumptions. We must develop a viable discipline of simulation to aid experimental and industrial application of software reliability engineering. This will require developing standard modeling components, connections, tools, and a body of knowledge to interpret the phenomena that are being modeled. This paper explains how and why simulation models of software reliability can ...
Abstract With the advent of VLSI (Very Large Scale Integration), the importance of CMOS (Compleme... more Abstract With the advent of VLSI (Very Large Scale Integration), the importance of CMOS (Complementary Metal Oxide Semiconductor) technology has increased. CMOS offers some very significant advantages over NMOS, and has emerged very competitive. Therefore, testability of CMOS devices is of considerable importance. CMOS devices exhibit some failure modes which are not adequately represented by the classical stuck-at fault model. A new fault model is introduced here to represent such faults. Leakage faults are specifically ...
A few religious communities of the world like Parsis and Jews have identified the threat to their... more A few religious communities of the world like Parsis and Jews have identified the threat to their existence. The Parsis have managed to survive after arriving in India. However today they are raising very few children and are on the verge of extinction. Half the Jewish population in USA marry outside their community. Studies show that most grandchildren of Jewish-non-Jewish marriage do not identify with Judaism. But they have at least recognized the problem.
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