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ORCIDHLDVT 2005: Napa Valley, CA, USA
- Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30 - December 2, 2005. IEEE Computer Society 2005, ISBN 0-7803-9571-9
Test, Fault & Error Modeling
- Charles H.-P. Wen
, Li-C. Wang, Kwang-Ting Cheng:
Simulation-based functional test generation for embedded processors. 3-10 - Chen He, Margarida F. Jacome, Gustavo de Veciana:
Scalable defect mapping and configuration of memory-based nanofabrics. 11-18 - Juan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil:
Improvement of fault injection techniques based on VHDL code modification. 19-26 - Jorge Campos, Hussain Al-Asaad:
MVP: a mutation-based validation paradigm. 27-34
Equivalence Verification
- Himyanshu Anand, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis:
Establishing latch correspondence for embedded circuits of PowerPC microprocessors. 37-44 - Feng Lu, Kwang-Ting (Tim) Cheng:
Sequential equivalence checking based on k-th invariants and circuit SAT solving. 45-51 - Manan Syal, Michael S. Hsiao:
VERISEC: verifying equivalence of sequential circuits using SAT. 52-59
System-Level Modeling & Co-Design
- Jean-Pierre Talpin, Sandeep Kumar Shukla:
Automated clock inference for stream function-based system level specifications. 63-70 - Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Cosimulation of ITRON-based embedded software with SystemC. 71-76
Validation Test Generation I
- Adriel Cheng, Cheng-Chew Lim, Atanas N. Parashkevov:
A software test program generator for verifying system-on-chips. 79-86 - Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. 87-93 - Kevin D. Rich, Shankar G. Govindaraju, Robert Shaw, David Dobrikin:
DVGen: a test generator for the transmeta Efficeon VLIW processor. 94-101
Validation Test Generation II
- Yoav Katz, Itai Jaeger, Roy Emek, Yossi Lichtenstein, Anita Devadason, Audrey Romonosky:
Reuse in system-level stimuli-generation. 105-111 - Shai Fine, Ari Freund, Itai Jaeger, Yehuda Naveh, Avi Ziv, Yishay Mansour:
Harnessing machine learning to improve the success rate of stimuli generation. 112-118
New Approaches in Simulation
- Qingwei Wu, Michael S. Hsiao:
A new simulation-based property checking algorithm based on partitioned alternative search space traversal. 121-126 - Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
Validating families of latency insensitive protocols. 127-134 - Dhiraj K. Pradhan, Ashutosh Kumar Singh, T. L. Rajaprabhu, Abusaleh M. Jabir:
GASIM: a fast Galois field based simulator for functional model. 135-142
Formal Verification
- Prakash Mohan Peranandam, Pradeep Kumar Nalla, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Overlap reduction in symbolic system traversal. 145-152 - Roope Kaivola, Armaghan Naik:
Formal verification of high-level conformance with symbolic simulation. 153-159 - Edward Smith:
A method for generation of GSTE assertion graphs. 160-167 - Zhenyu Chen, Conghua Zhou, Decheng Ding:
Automatic abstraction refinement for Petri nets verification. 168-174
SAT & SAT Applications
- Chia-Chih Yen, Jing-Yang Jou:
An optimum algorithm for compacting error traces for efficient functional debugging. 177-183 - Vishnu C. Vimjam, Michael S. Hsiao:
Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking. 184-191 - Domagoj Babic, Jesse D. Bingham, Alan J. Hu:
B-cubing theory: new possibilities for efficient SAT-solving. 192-199
Security
- David D. Hwang, Shenglin Yang, Ingrid Verbauwhede, Patrick Schaumont:
Multilevel design validation in a secure embedded system. 203-210 - Huiyun Li, A. Theodore Markettos, Simon W. Moore:
Security evaluation against electromagnetic analysis at design time. 211-218
Coverage
- Íñigo Ugarte, Pablo Sanchez:
Formal meaning of coverage metrics in simulation-based hardware design verification. 221-228 - Hezi Azatchi, Laurent Fournier, Avi Ziv, Keren Zohar:
Advanced analysis techniques for cross-product coverage. 229-236 - Katell Morin-Allory, Dominique Borrione:
A proof of correctness for the construction of property monitors. 237-244
Panel
- Andrew Piziali, Avi Ziv:
Panel: Functional coverage - is your design exposed? 247
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