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ORCID21st LATS 2020: Maceio, Brazil
- IEEE Latin-American Test Symposium, LATS 2020, Maceio, Brazil, March 30 - April 2, 2020. IEEE 2020, ISBN 978-1-7281-8731-0
- Cleiton Magano Marques
, Cristina Meinhardt, Paulo F. Butzen:
Soft Error Reliability of SRAM cells during the three operation states. 1-6 - Jacopo Sini, M. D'Auria, Massimo Violante:
Towards Vehicle-Level Simulator Aided Failure Mode, Effect, and Diagnostic Analysis of Automotive Power Electronics Items. 1-6 - Carlos Bernal, Manuel Jiménez, Chris Aquino, Raul Cedres:
A Test Architecture and VIE to Characterize Dielectric Absorption in Small Capacitors. 1-5 - Bruno L. Costa, Carlos J. González, Rafael Galhardo Vaz, Odair Lelis Gonçalez, Tiago R. Balen:
Influence of sampling frequency on TID response of SAR ADCs. 1-6 - Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters. 1-6 - João Carlos Britto Filho, Marcelo Lubaszewski:
A Highly Reliable Wearable Device for Fall Detection. 1-7 - Davide Piumatti, Matteo Vincenzo Quitadamo, Matteo Sonza Reorda, Franco Fiori:
Testing Heatsink Faults in Power Transistors by means of Thermal Model. 1-6 - Matheus Deon Bordignon, Rodolfo Adamshuk Silva:
Mutation Operators for Concurrent Programs in Elixir. 1-6 - Alexander Aponte-Moreno, José Isaza-González, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle:
An Experimental Comparison of Fault Injection Tools for Microprocessor-based Systems. 1-6 - Israel C. Lopes, Vincent Pouget, Frederic Wrobel, Frédéric Saigné, Antoine D. Touboul, Ketil Røed:
Development and evaluation of a flexible instrumentation layer for system-level testing of radiation effects. 1-6 - Moabe F. Domingos, George H. Castro, Jarbas Silveira, Felipe G. A. e Silva, M. K. D. Pereira, Pedro Lima:
MMS: A Software for Error Monitoring in Memories Protected by ECC. 1-6 - David Ruiz Falcó, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi:
Soft error reliability predictor based on a Deep Feedforward Neural Network. 1-5 - Salem Abdennadher, Kyle Tripician, Senthil Singaravelu:
At Speed Testing Challenges and Solutions for 56Gbps and 112Gbps PAM4 SerDes. 1-5 - Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzèrho, Francois Lefevre, I. Gorenflot:
Implementing indirect test of RF circuits without compromising test quality: a practical case study. 1-6 - Hardi Selg, Maksim Jenihhin, Peeter Ellervee:
Wafer-Level Die Re-Test Success Prediction Using Machine Learning. 1-5 - Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea:
Evaluating the Code Encryption Effects on Memory Fault Resilience. 1-6 - Marcio Gonçalves, José Rodrigo Azambuja, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU. 1-6 - Ghislain Takam Tchendjou, Emmanuel Simeu:
Parametric faults detection and concealment on imager with FPGA implementation. 1-6 - Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Leticia Bolzani Poehls, Tiago R. Balen:
Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects. 1-6 - Zahira Perez, Javier Mesalles, Hector Villacorta, Fabian Vargas, Víctor H. Champac:
Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells. 1-6 - Pedro Lima, Caio Vieira, Jorge Reis, Alexandre Almeida, Jarbas Silveira, Roger C. Goerl, César A. M. Marcon:
Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC. 1-5 - Raphael Segabinazzi Ferreira, Jörg Nolte, Fabian Vargas, Nevin George, Michael Hübner:
Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications. 1-6 - Ievgen Kabin, Zoya Dyka, Marcin Aftowicz, Dan Klann, Peter Langendörfer:
Resistance of the Montgomery kP Algorithm against Simple SCA: Theory and Practice. 1-6 - Ricardo A. L. Reis, Cristina Meinhardt, Alexandra L. Zimpeck, Leonardo Heitich Brendler, Leonardo B. Moraes:
Circuit Level Design Methods to Mitigate Soft Errors. 1-3
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