default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID17th PATMOS 2007: Gothenburg, Sweden
- Nadine Azémard, Lars J. Svensson:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Lecture Notes in Computer Science 4644, Springer 2007, ISBN 978-3-540-74441-2
High-Level Design (1)
- Lazaros Papadopoulos, Dimitrios Soudris:
System-Level Application-Specific NoC Design for Network and Multimedia Applications. 1-9 - Nicolas Fournel, Antoine Fraboulet, Paul Feautrier:
Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements. 10-19 - Ioannis Panagopoulos, Christos Pavlatos, George Manis, George K. Papakonstantinou:
A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms. 20-30 - Julien Delorme:
An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture. 31-42
Low Power Design Techniques
- Ming-che Lai, Zhiying Wang, Jianjun Guo, Kui Dai, Shen Li:
Template Vertical Dictionary-Based Program Compression Scheme on the TTA. 43-52 - Delong Shang, Chi-Hoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeong-Hoon Oh, Seongwoon Kim, Alexandre Yakovlev:
Asynchronous Functional Coupling for Low Power Sensor Network Processors. 53-63 - Noureddine Chabini:
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. 64-74 - Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
:
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. 75-85 - Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li:
The Design and Implementation of a Power Efficient Embedded SRAM. 86-96
Statistical Static Timing Analysis
- Björn Lipka, Ulrich Kleine:
Design of a Linear Power Amplifier with +/-1.5V Power Supply Using ALADIN. 97-106 - Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling Time Minimization of Operational Amplifiers. 107-116 - Cosmin Popa:
Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs. 117-124 - Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula:
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. 125-137 - V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine:
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. 138-147 - Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang:
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. 148-159
Power Modeling and Optimization
- Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. 160-170 - Marko Hoyer, Domenik Helms, Wolfgang Nebel:
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. 171-180 - Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija:
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. 181-190 - C. R. Parthasarathy, Alain Bravaix, Chloe Guérin, Mickael Denais, Vincent Huard:
Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation. 191-200
Low Power Routing Optimization
- Davide Pandini, Guido A. Repetto, Vincenzo Sinisi:
Clock Distribution Techniques for Low-EMI Design. 201-210 - Mini Nanua, David T. Blaauw:
Crosstalk Waveform Modeling Using Wave Fitting. 211-221 - Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu:
Weakness Identification for Effective Repair of Power Distribution Network. 222-231 - Prassanna Sithambaram, Alberto Macii, Enrico Macii:
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses. 232-241 - Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner:
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. 242-254
High Level Design (2)
- Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh:
Soft Error-Aware Power Optimization Using Gate Sizing. 255-267 - Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger:
Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices. 268-277 - Sven Rosinger, Domenik Helms, Wolfgang Nebel:
RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. 278-287 - Allan Crone, Gabriel Chidolue:
Functional Verification of Low Power Designs at RTL. 288-299 - Zoltán Herczeg, Ákos Kiss, Daniel Schmidt, Norbert Wehn, Tibor Gyimóthy:
XEEMU: An Improved XScale Power Simulator. 300-309
Security and Asynchronous Design
- Maurice Keller, William P. Marnane:
Low Power Elliptic Curve Cryptography. 310-319 - Jian Ruan, Zhiying Wang, Kui Dai, Yong Li:
Design and Test of Self-checking Asynchronous Control Circuit. 320-329 - Behnam Ghavami, Hossein Pedram:
An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips. 330-339 - Alin Razafindraibe, Michel Robert, Philippe Maurine:
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. 340-351
Low Power Applications
- Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. 352-362 - Hendrik Eeckhaut, Harald Devos, Dirk Stroobandt:
The Energy Scalability of Wavelet-Based, Scalable Video Decoding. 363-372 - Miguel Peón Quirós, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption. 373-383
Poster1 - Modeling and Optimization
- Toshinori Sato, Yuji Kunitake:
Exploiting Input Variations for Energy Reduction. 384-393 - Alin Razafindraibe, Philippe Maurine:
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. 394-403 - David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Static Power Consumption in CMOS Gates Using Independent Bodies. 404-412 - Fabrice Guigues, Edith Kussener, Benjamin Duval, Hervé Barthélemy:
Moderate Inversion: Highlights for Low Voltage Design. 413-422 - Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui:
On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems. 423-432 - Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest:
Semi Custom Design: A Case Study on SIMD Shufflers. 433-442
Poster 2 - High Level Design
- Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Majid Sarrafzadeh:
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models. 443-452 - Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki:
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. 453-462 - Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram:
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. 463-473 - Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. 474-484 - Christophe Lucarz, Marco Mattavelli:
A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning. 485-494 - Henrik Lipskoch, Karsten Albers, Frank Slomka:
Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems. 495-504 - Nikolas Kroupis, Dimitrios Soudris:
Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate. 505-515
Poster 3 - Low Power Techniques and Applications
- Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti:
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. 516-525 - Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Johansson, Per Gunnar Kjeldsberg:
Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data. 526-535 - Jon Alfredsson, Snorre Aunet:
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. 536-545 - Charalambos Basetas, Ioannis Kouretas, Vassilis Paliouras:
Low-Power Digital Filtering Based on the Logarithmic Number System. 546-555 - Sylvain Miermont, Pascal Vivet, Marc Renaudin:
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. 556-565 - Henrik Eriksson:
Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers. 566-575
Keynotes
- J. M. Daga:
Design and Industrialization Challenges of Memory Dominated SOCs. 576 - Davide Pandini:
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies. 577 - Christer Svensson:
Analog Power Modelling. 578
Industrial Session - Design Challenges in Real-Life Projects
- F. Dahlgren:
Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms. 579 - Anders Emrich:
System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. 580
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-10 21:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
