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ORCIDIEEE Design & Test of Computers, Volume 4
Volume 4, Number 1, February 1987
- Randy H. Katz, Rajiv Bhateja, Ellis E. Chang, David Gedye, Vony Trijanto:
Design Version Management. 12-22 - Sy-Yen Kuo
, W. Kent Fuchs:
Efficient Spare Allocation for Reconfigurable Arrays. 24-31 - Hiroyuki Watanabe:
Flute an Expert Floor Planner for Full-Custom VLSI Design. 32-41 - Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita:
Built-In Self-Testing RAM: A Practical Alternative. 42-51 - Sudhakar M. Reddy, Ramaswami Dandapani:
Scan Design Using Standard Flip-Flops. 52-54
Volume 4, Number 2, April 1987
- Randall Kramer:
Testing Mixed-Signal Devices. 12-20 - Mark R. Barber, Walter I. Satre:
Timing Accuracy in Modern ATE. 22-30 - John A. Waicukauski, Eric Lindbloom, Barry K. Rosen, Vijay S. Iyengar:
Transition Fault Simulation. 32-38 - Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke:
Aliasing Errors in Signature Analysis Registers. 39-45 - Alexander Miczo, Dipti Mohapatra, Scott Perkins, Katie Kaufman, Ken Huang:
The Effects of Modeling on Simulator Performance. 46-54
Volume 4, Number 3, June 1987
- David R. Ditzel, Alan D. Berenbaum:
Using CAD Tools in the Design of CRISP. 21-31 - Hu H. Chao, Shauchi Ong, Mon Yen (Mike) Tsai, Feng-Hsien W. Shih, Kelvin W. Lewis, Jeffrey Yuh-Fong Tang, Cynthia A. Trempel, Hwa Nien Yu, Peter E. McCormick, Clinton V. Davis Jr., Andrew L. Diamond, Thomas J. Medve, John C. L. Hou:
Designing the Micro/370. 32-40 - Patrick P. Gelsinger:
Design And Test of the 80386. 42-50 - Shoji Horiguchi, Hiroshi Yoshimura, Mitsuyoshi Nagatani, Kennosuke Fukami:
The Design of Dedicated 32-Bit Processors. 52-58
Volume 4, Number 4, August 1987
- John P. Hayes:
An Introduction to Switch-Level Modeling. 18-25 - Randal E. Bryant:
A Survey of Switch-Level Algorithms. 26-40 - Dick L. Liu, Edward J. McCluskey:
Designing CMOS Circuits for Switch-Level Testability. 42-49 - Paul H. Bardell:
TTTC 10th Anniversary. 50-54
Volume 4, Number 5, October 1987
- Frederica Darema, Gregory F. Pfister:
Multipurpose Parallelism for VLSI Cad on the RP3. 19-27 - Prathima Agrawal, William J. Dally, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar, Raffi Tutundjian:
MARS: A Multiprocessor-Based Programmable Accelerator. 28-36 - Thomas Ryan, Edwin Rogers:
An Isma Lee Router Accelerator. 38-45
Volume 4, Number 6, December 1987
- Lindsay Kleeman, Antonio Cantoni:
Metastable Behavior in Digital Systems. 4-19 - Kazuhiro Ueda, Hitoshi Kitazawa, Tohru Adachi, Ikuo Harada:
Top-Down Layout for Hierarchical Custom Design. 22-29 - Janusz Rajski, Vinod K. Agarwal:
Testing and Applications of Inverter-Free PLAs. 30-40 - Walid A. Najjar, Jean-Luc Jezouin, Jean-Luc Gaudiot:
Parallel Discrete-Event Simulation. 41-44
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