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2020 – today
- 2022
[j6]Niko Zurstraßen
, Lukas Jünger, Tim Kogel, Holger Keding, Rainer Leupers:
AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators. Int. J. Parallel Program. 50(2): 295-318 (2022)- 2020
- [j5]Kun-Chih Chen, Masoumeh Ebrahimi, Maurizio Palesi, Tim Kogel:
Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 265-267 (2020) - [j4]Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi:
An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 268-282 (2020) - [c20]Lukas Jünger, Niko Zurstraßen, Tim Kogel, Holger Keding, Rainer Leupers:
AMAIX: A Generic Analytical Model for Deep Learning Accelerators. SAMOS 2020: 36-51
2010 – 2019
- 2017
- [p1]Tim Kogel:
Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis. Handbook of Hardware/Software Codesign 2017: 1127-1159 - 2012
- [c19]Rainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel:
Virtual platforms: Breaking new grounds. DATE 2012: 685-690 - 2010
- [c18]Tor E. Jeremiassen, Tim Kogel, Andrés Takach, Grant Martin, Adam Donlin, Karamvir Chatha:
From ESL 2010 to ESL 2015. CODES+ISSS 2010: 61-62
2000 – 2009
- 2009
- [c17]Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach:
From milliwatts to megawatts: system level power challenge. DAC 2009: 750-751 - 2008
- [j3]Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr:
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. Int. J. Embed. Syst. 3(3): 109-118 (2008) - [j2]Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr:
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. Int. J. Embed. Syst. 3(3): 150-159 (2008) - [c16]Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil D. Dutt, Giovanni Mancini:
ESL hand-off: fact or EDA fiction? DAC 2008: 310-312 - [c15]Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel:
Heterogeneous System-level Specification Using SystemC. DATE 2008 - 2006
- [b1]Tim Kogel, Rainer Leupers, Heinrich Meyr:
Integrated system-level modeling of network-on-chip enabled multi-processor platforms. RWTH Aachen University, Germany, Kluwer 2006, ISBN 978-1-4020-4825-8, pp. I-XIV, 1-199 - [c14]Tim Kogel, Matthew Braun:
Virtual prototyping of embedded platforms for wireless and multimedia. DATE 2006: 488-490 - 2005
- [c13]Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285 - [c12]Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel:
Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254 - [c11]Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout:
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE 2005: 876-881 - [c10]Tim Kogel, Anssi Haverinen:
OCP TLM for Architectural Modelling. FDL 2005: 225-244 - 2004
- [c9]Tim Kogel, Heinrich Meyr:
Heterogeneous MP-SoC: the solution to energy-efficient signal processing. DAC 2004: 686-691 - [c8]Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl:
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263 - [c7]Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren:
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE 2004: 1276-1283 - [c6]Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148 - [c5]Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452 - 2003
- [c4]Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann:
Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization. ASAP 2003: 161-171 - [c3]Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 - [c2]Manoj Ariyamparambath, Denis Bussaglia, Bernd Reinkemeier, Tim Kogel, Torsten Kempf:
A highly efficient modeling style for heterogeneous bus architectures. SoC 2003: 83-87 - 2001
- [j1]Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr:
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1338-1354 (2001) - [c1]Andreas Hoffmann, Tim Kogel, Heinrich Meyr:
A framework for fast hardware-software co-simulation. DATE 2001: 760-765
Coauthor Index
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