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ORCIDZiran Zhu
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2020 – today
- 2025
[j18]Disi Lin, Chuandong Chen, Rongshan Wei, Qinghai Liu, Huan He, Ziran Zhu, Zhifeng Lin
, Jianli Chen:
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB. Integr. 100: 102270 (2025)- 2024
- [j17]Zijun Li, Ziran Zhu, Huan He, Jianli Chen:
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs. Integr. 94: 102098 (2024) - [j16]Xiqiong Bai, Yilu Chen, Zhifeng Lin, Min Wei, Zhijie Cai, Ziran Zhu, Jianli Chen:
A fast and high-performance global router with enhanced congestion control. Integr. 99: 102263 (2024) - [j15]Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, Yao-Wen Chang:
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 956-969 (2024) - [j14]Ziran Zhu, Fuheng Shen, Yangjie Mei, Jianli Chen, Jun Yang:
An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 161-165 (2024) - [j13]Ziran Zhu, Yuejian Shi, Yangjie Mei, Fuheng Shen, Hong Liu, Jun Yang:
High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1151-1155 (2024) - [j12]Hao Gu, Jian Gu, Keyu Peng, Ziran Zhu, Ning Xu, Xin Geng, Jun Yang:
LAMPlace: Legalization-Aided Reinforcement Learning-Based Macro Placement for Mixed-Size Designs With Preplaced Blocks. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3770-3774 (2024) - [j11]Ziran Zhu, Yilin Li, Miaodi Su, Shu Zhang, Haiyuan Su, Yifeng Xiao, Huan He, Jianli Chen, Yao-Wen Chang:
Subgraph matching-based reference placement for printed circuit board designs. J. Supercomput. 80(16): 24324-24357 (2024) - [c17]Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang:
Variational Label-Correlation Enhancement for Congestion Prediction. ASPDAC 2024: 466-471 - [c16]Hao Gu, Jian Gu, Keyu Peng, Jun Yang, Ziran Zhu:
Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints. DAC 2024: 348:1-348:2 - [c15]Tongda Xu, Ziran Zhu, Dailan He, Yanghao Li, Lina Guo, Yuanyuan Wang, Zhe Wang, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang:
Idempotence and Perceptual Image Compression. ICLR 2024 - [c14]Ziran Zhu, Tongda Xu, Ling Li, Yan Wang:
Noise Dimension of GAN: An Image Compression Perspective. ICME 2024: 1-6 - [i4]Tongda Xu, Ziran Zhu, Dailan He, Yanghao Li, Lina Guo, Yuanyuan Wang, Zhe Wang, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang:
Idempotence and Perceptual Image Compression. CoRR abs/2401.08920 (2024) - [i3]Ziran Zhu, Tongda Xu, Ling Li, Yan Wang:
Noise Dimension of GAN: An Image Compression Perspective. CoRR abs/2403.09196 (2024) - [i2]Tongda Xu, Ziran Zhu, Dailan He, Yuanyuan Wang, Ming Sun, Ning Li, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang:
Consistency Models Improve Diffusion Inverse Solvers. CoRR abs/2403.12063 (2024) - 2023
- [c13]Chuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu, Jianli Chen:
Efficient Global Optimization for Large Scaled Ordered Escape Routing. ASP-DAC 2023: 535-540 - [c12]Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang:
Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints. DAC 2023: 1-6 - [c11]Ke Liu, Jian Gu, Hao Gu, Ziran Zhu:
A Hybrid Reinforcement Learning and Genetic Algorithm for VLSI Floorplanning. ICMLC 2023: 412-418 - [i1]Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang:
Variational Label-Correlation Enhancement for Congestion Prediction. CoRR abs/2308.00529 (2023) - 2022
- [j10]Jianli Chen, Ziran Zhu, Longkun Guo, Yu-Wei Tseng, Yao-Wen Chang:
Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1103-1115 (2022) - [j9]Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Yu, Wenxing Zhu, Yao-Wen Chang:
Timing-Aware Fill Insertions With Design-Rule and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3529-3542 (2022) - [j8]Jianli Chen, Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5541-5553 (2022) - [c10]Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang:
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. ASP-DAC 2022: 172-177 - [c9]Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang:
High-performance placement for large-scale heterogeneous FPGAs with clock constraints. DAC 2022: 643-648 - [c8]Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang:
Subgraph matching based reference placement for PCB designs: late breaking results. DAC 2022: 1400-1401 - [c7]Ziran Zhu, Fuheng Shen, Yangjie Mei, Zhipeng Huang, Jianli Chen, Jun Yang:
A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints. ICCAD 2022: 129:1-129:9 - 2021
- [j7]Ziran Zhu, Zhipeng Huang, Jianli Chen, Longkun Guo:
Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles. Complex. 2021: 8843271:1-8843271:12 (2021) - [j6]Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization. ACM Trans. Design Autom. Electr. Syst. 26(2): 15:1-15:28 (2021) - [c6]Zhipeng Huang, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Yu, Jianli Chen:
Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints. DAC 2021: 1362-1363 - [c5]Xiqiong Bai, Ziran Zhu, Peng Zou, Lichong Sun, Jianli Chen:
Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. DAC 2021: 1364-1365 - 2020
- [j5]Zhipeng Huang, Zhifeng Lin, Ziran Zhu, Jianli Chen:
An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning. IEEE Access 8: 50911-50920 (2020) - [j4]Ziran Zhu, Zhipeng Huang, Peng Yang, Wenxing Zhu, Jianli Chen, Hanbin Zhou, Senhua Dong:
Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect. Integr. 71: 1-10 (2020) - [j3]Ziran Zhu, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Mixed-Cell-Height Legalization Considering Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5128-5141 (2020) - [c4]Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang:
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. DAC 2020: 1-6
2010 – 2019
- 2018
- [c3]Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Generalized augmented lagrangian and its applications to VLSI global placement. DAC 2018: 149:1-149:6 - [c2]Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Mixed-cell-height legalization considering technology and region constraints. ICCAD 2018: 65 - 2017
- [j2]Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu:
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning. Integr. 58: 245-252 (2017) - [j1]Xingquan Li, Ziran Zhu, Wenxing Zhu:
Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition. IEEE Trans. Computers 66(2): 285-298 (2017) - [c1]Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs. DAC 2017: 52:1-52:6
Coauthor Index
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