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2020 – today
- 2024
[j3]Shixin Chen
, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli:
Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1638-1649 (2024)- [j2]Genggeng Liu, Yuhan Zhu, Zhen Zhuang, Zhenyu Pei, Min Gan, Xing Huang, Wenzhong Guo:
A Robust Multilayer X-Architecture Global Routing System Based on Particle Swarm Optimization. IEEE Trans. Syst. Man Cybern. Syst. 54(9): 5627-5640 (2024) - 2023
- [c9]Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong:
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. ICCAD 2023: 1-9 - [i2]Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli:
Floorplet: Performance-aware Floorplan Framework for Chiplet Integration. CoRR abs/2308.01672 (2023) - 2022
- [c8]Zhen Zhuang, Genggeng Liu, Tsung-Yi Ho, Bei Yu, Wenzhong Guo:
TRADER: A Practical Track-Assignment-Based Detailed Router. DATE 2022: 766-771 - [c7]Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho:
Multi-Package Co-Design for Chiplet Integration. ICCAD 2022: 114:1-114:9 - [c6]Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang:
SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. VLSI-SoC 2022: 1-6 - 2021
- [c5]Zhen Zhuang, Xing Huang, Genggeng Liu, Wenzhong Guo, Weikang Qian, Wen-Hao Liu:
ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification. DATE 2021: 1570-1573 - 2020
- [j1]Genggeng Liu, Zhisheng Chen, Zhen Zhuang, Wenzhong Guo, Guolong Chen:
A unified algorithm based on HTS and self-adapting PSO for the construction of octagonal and rectilinear SMT. Soft Comput. 24(6): 3943-3961 (2020) - [c4]Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang:
MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. DATE 2020: 586-591 - [c3]Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo:
MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique. ACM Great Lakes Symposium on VLSI 2020: 107-112
2010 – 2019
- 2019
- [c2]Genggeng Liu, Zhen Zhuang, Wenzhong Guo, Ting-Chi Wang:
RDTA: An Efficient Routability-Driven Track Assignment Algorithm. ACM Great Lakes Symposium on VLSI 2019: 315-318 - [c1]Hailin Wu, Saijuan Xu, Zhen Zhuang, Genggeng Liu:
X-Architecture Steiner Minimal Tree Construction Based on Discrete Differential Evolution. ICNC-FSKD 2019: 433-442 - 2018
- [i1]Genggeng Liu, Zhen Zhuang, Wenzhong Guo, Naixue Xiong, Guolong Chen:
A novel particle swarm optimizer with multi-stage transformation and genetic operation for VLSI routing. CoRR abs/1811.10225 (2018)
Coauthor Index
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