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ORCIDHikaru Takayashiki
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2020 – today
- 2023
[c5]Hikaru Takayashiki
, Hotaka Yagi, Hiroki Nishimoto, Naoki Yoshifuji:
A New Sparse GEneral Matrix-matrix Multiplication Method for Long Vector Architecture by Hierarchical Row Merging. SC Workshops 2023: 756-759- 2022
- [j3]Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Metadata Prefetching Mechanism for Hybrid Memory Architectures. IEICE Trans. Electron. 105-C(6): 232-243 (2022) - [c4]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation. IA3@SC 2022: 1-8 - 2021
- [c3]Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Metadata Prefetching Mechanism for Hybrid Memory Architectures. COOL CHIPS 2021: 1-3 - [c2]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
Register Flush-free Runahead Execution for Modern Vector Processors. SBAC-PAD 2021: 114-125
2010 – 2019
- 2019
- [j2]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Skewed Multi-banked Cache for Many-core Vector Processors. Supercomput. Front. Innov. 6(3): 86-101 (2019) - [j1]Masayuki Sato, Takuya Toyoshima, Hikaru Takayashiki, Ryusuke Egawa, Hiroaki Kobayashi:
An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems. Supercomput. Front. Innov. 6(4): 4-19 (2019) - [c1]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Hardware Prefetching Mechanism for Vector Gather Instructions. IA3@SC 2019: 59-66
Coauthor Index
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