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Mohsen Saneei
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2020 – today
- 2021
- [j14]Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam:
Jitter Modeling in Digital CDR with Quantization Noise Analysis. Circuits Syst. Signal Process. 40(8): 3884-3906 (2021) - [j13]Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam:
Evaluation of multi-level Bang-Bang phase detector with metastability effect using Markov chain. Microelectron. J. 115: 105169 (2021) - 2020
- [j12]Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam:
Jitter and metastability analysis and modeling of multilevel bang-bang phase detector. Int. J. Circuit Theory Appl. 48(8): 1371-1385 (2020)
2010 – 2019
- 2019
- [j11]Ramin Razmdideh, Mohsen Saneei:
All-digital delay line-based time difference amplifier in 65 nm CMOS technology. IET Circuits Devices Syst. 13(4): 421-427 (2019) - [j10]Shirin Askari, Mohsen Saneei:
Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications. Int. J. Circuit Theory Appl. 47(2): 204-216 (2019) - 2018
- [j9]Sanaz Salem, Hamed Zandevakili, Ali Mahani, Mohsen Saneei:
Fault-tolerant delay cell for ring oscillator application in 65 nm CMOS technology. IET Circuits Devices Syst. 12(3): 233-241 (2018) - [j8]Ramin Razmdideh, Mohsen Saneei:
Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology. Int. J. Circuit Theory Appl. 46(6): 1264-1271 (2018) - 2015
- [j7]Asma Dehghani, Mohsen Saneei, Ali Mahani:
Time-to-digital convertor based on resolution control. IET Circuits Devices Syst. 9(5): 370-376 (2015) - [j6]Ramin Razmdideh, Mohsen Saneei:
A novel low power and high speed double edge explicit pulse triggered level converter flip-flop. Int. J. Circuit Theory Appl. 43(4): 516-523 (2015) - [j5]Ramin Razmdideh, Mohsen Saneei:
Two novel low power and very high speed pulse triggered flip-flops. Int. J. Circuit Theory Appl. 43(12): 1925-1934 (2015) - [j4]Ramin Razmdideh, Ali Mahani, Mohsen Saneei:
New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption. J. Circuits Syst. Comput. 24(10): 1550159:1-1550159:11 (2015) - 2013
- [j3]Hamed Zandevakili, Ali Mahani, Mohsen Saneei:
Probabilistic Transfer Matrix with mixed Binary-Decimal Coding for Logic Circuit Reliability Analysis. J. Circuits Syst. Comput. 22(8) (2013)
2000 – 2009
- 2009
- [j2]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Sign Bit Reduction Encoding For Low Power Applications. J. Signal Process. Syst. 57(3): 321-329 (2009) - 2007
- [j1]Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram:
Fast INC-XOR codec for low-power address buses. IET Comput. Digit. Tech. 1(5): 625-626 (2007) - 2006
- [c3]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Low-power and low-latency cluster topology for local traffic NoCs. ISCAS 2006 - [c2]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Serial Bus Encoding for Low Power Application. SoC 2006: 1-4 - 2005
- [c1]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Sign bit reduction encoding for low power applications. DAC 2005: 214-217
Coauthor Index
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