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2020 – today
- 2024
[c13]Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo-Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao:
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. ISSCC 2024: 338-340- 2022
- [c12]Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang, Afshin Momtaz:
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology. ISSCC 2022: 120-122
2010 – 2019
- 2016
- [j9]Namik Kocaman, Tamer A. Ali, Lakshmi P. Rao
, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz:
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS. IEEE J. Solid State Circuits 51(4): 881-892 (2016) - 2015
- [c11]Ali Nazemi, Kangmin Hu, Burak Çatli, Delong Cui, Ullas Singh, Tim He, Zhi Chao Huang, Bo Zhang, Afshin Momtaz, Jun Cao:
3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS. ISSCC 2015: 1-3 - [c10]Tamer A. Ali, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz, Namik Kocaman:
A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS. VLSIC 2015: 348- - 2014
- [j8]Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS. IEEE J. Solid State Circuits 49(12): 3116-3129 (2014) - [c9]Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao:
2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS. ISSCC 2014: 40-41 - [c8]Adesh Garg, Ullas Singh, Nick Huang, Wayne Wong, Bin Liu, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS. VLSIC 2014: 1-2 - 2013
- [j7]Namik Kocaman, Siavash Fallahi, Mahyar Kargar, Mehdi Khanpour, Ali Nazemi, Ullas Singh, Afshin Momtaz:
An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition. IEEE J. Solid State Circuits 48(8): 1875-1884 (2013) - [j6]Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao:
A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. IEEE J. Solid State Circuits 48(12): 3219-3228 (2013) - [c7]Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. ISSCC 2013: 32-33 - 2012
- [j5]Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Wei Zhang, Tamer A. Ali, Nick Huang, Bo Zhang, Afshin Momtaz, Jun Cao:
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. IEEE J. Solid State Circuits 47(12): 3249-3260 (2012) - [c6]Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Tamer A. Ali, Nick Huang, Wei Zhang, Bo Zhang, Afshin Momtaz, Jun Cao:
A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. ISSCC 2012: 330-332 - 2011
- [j4]Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz:
11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications. IEEE J. Solid State Circuits 46(12): 3089-3100 (2011) - [c5]Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz:
11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. ISSCC 2011: 142-144 - 2010
- [j3]Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. IEEE J. Solid State Circuits 45(6): 1172-1185 (2010)
2000 – 2009
- 2009
- [c4]Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. ISSCC 2009: 370-371 - 2006
- [j2]Ullas Singh, Lijun Li, Michael M. Green:
A 34 Gb/s Distributed 2: 1 MUX and CMU Using 0.18$muhbox m$CMOS. IEEE J. Solid State Circuits 41(9): 2067-2076 (2006) - 2005
- [j1]Ullas Singh, Michael M. Green:
High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz. IEEE J. Solid State Circuits 40(8): 1658-1661 (2005) - 2003
- [c3]Michael M. Green, Ullas Singh:
Design of CMOS CML circuits for high-speed broadband communications. ISCAS (2) 2003: 204-207 - 2002
- [c2]Ullas Singh, Michael Green:
Dynamics of high-frequency CMOS dividers. ISCAS (5) 2002: 421-424 - 2001
- [c1]Ullas Singh, Michael Green:
New structures for very high-frequency CMOS clock dividers. ISCAS (4) 2001: 622-625
Coauthor Index
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