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2020 – today
- 2024
[j3]Lu Zhang
, Dejun Mu, Jingyu Wang, Ruoyang Liu, Yifan He, Yaolei Li, Yu Tai, Shengbing Zhang, Xiaoya Fan, Huazhong Yang, Yongpan Liu:
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2916-2929 (2024)- [c3]Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. ISSCC 2024: 578-580 - 2023
- [j2]Lu Zhang, Dejun Mu, Yuxuan Huang, Jingyu Wang, Yifan He, Yaolei Li, Lizhou Liu, Kaiwei Zou, Huazhong Yang, Yongpan Liu:
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1124-1128 (2023) - [j1]Yaolei Li, Jinshan Yue, Jingyu Wang, Chen Tang, Yifan He, Wenbin Jia, Kaiwei Zou, Lu Zhang, Huazhong Yang, Yongpan Liu:
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1179-1183 (2023) - [c2]Hedi Wang, Zengwei Wang, Yaolei Li, Chen Tang, Jinxu Gao, Huazhong Yang, Yongpan Liu:
A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation. A-SSCC 2023: 1-3 - [c1]Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu:
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. VLSI Technology and Circuits 2023: 1-2
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