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2000 – 2009
- 2007
[i1]Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
:
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. CoRR abs/0710.4722 (2007)- 2005
- [c3]Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee:
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. DATE 2005: 279-280 - 2002
- [j3]Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen:
Design of an Inter-plane Circuit for Clocked PLAs. VLSI Design 14(4): 373-381 (2002) - 2001
- [j2]Chua-Chin Wang, Cheng-Fa Tsai, Yu-Tsun Chien:
Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. J. Inf. Sci. Eng. 17(2): 313-324 (2001) - 2000
- [j1]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. VLSI Design 11(2): 107-113 (2000) - [c2]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
Design of an inter-plane circuit for clocked PLAs. ISCAS 2000: 281-284
1990 – 1999
- 1999
- [c1]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. ISCAS (2) 1999: 528-531
Coauthor Index
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