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ORCIDRamachandra Achar
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2020 – today
- 2024
[c22]Anuj Mathur, Ramachandra Achar:
Recognition of Electronic Component Orientations from Hand-Drawn Circuit Schematics through a Two Stage Machine Learning System. NewCAS 2024: 26-29- [i2]Supriya Adhikary, Wai-Kong Lee, Angshuman Karmakar, Yongwoo Lee, Seong Oun Hwang, Ramachandra Achar:
cuTraNTT: A Novel Transposed Number Theoretic Transform Targeting Low Latency Homomorphic Encryption for IoT Applications. IACR Cryptol. ePrint Arch. 2024: 1729 (2024) - 2023
- [c21]Ahsan Javaid, Ramachandra Achar:
PSIJ Transfer Function Response Prediction via NARNET and KBNNs. NEWCAS 2023: 1-3 - 2022
- [j25]Wai-Kong Lee
, Ramachandra Achar:
Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation. IEEE Access 10: 78993-79003 (2022) - [j24]Muhammed Suhail Illikkal, Jai Narayan Tripathi, Vijender Kumar Sharma, Hitesh Shrimali, Ramachandra Achar:
Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters. IEEE Access 10: 100172-100177 (2022) - [j23]Wai-Kong Lee, Hwajeong Seo, Seong Oun Hwang, Ramachandra Achar, Angshuman Karmakar, Jose Maria Bermudo Mera:
DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3591-3604 (2022) - 2021
- [j22]Wai-Kong Lee, Ramachandra Achar:
GPU-Accelerated Adaptive PCBSO Mode-Based Hybrid RLA for Sparse LU Factorization in Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2320-2330 (2021) - [i1]Wai-Kong Lee, Hwajeong Seo, Seong Oun Hwang, Angshuman Karmakar, Jose Maria Bermudo Mera, Ramachandra Achar:
DPCrypto: Acceleration of Post-quantum Cryptographic Algorithms using Dot-Product Instruction on GPUs. IACR Cryptol. ePrint Arch. 2021: 1389 (2021) - 2020
- [j21]Wei Pau Kiat, Kai Ming Mok, Wai-Kong Lee, Hock Guan Goh, Ramachandra Achar:
An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications. Microprocess. Microsystems 73: 102966 (2020) - [c20]Srinidhi Ganeshan, Naveen Kumar Elumalai, Ramachandra Achar:
A Comparative Study of MAGMA and cuBLAS Libraries for GPU based Vector Fitting. LASCAS 2020: 1-4
2010 – 2019
- 2019
- [j20]Jai Narayan Tripathi, Muhammed Suhail Illikkal, Hitesh Shrimali, Ramachandra Achar:
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers. IEEE Access 7: 125240-125252 (2019) - [c19]Ihsan Erdin, Ramachandra Achar:
A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures. LASCAS 2019: 25-26 - 2018
- [j19]Jai Narayan Tripathi, Ramachandra Achar, Rakesh Malik:
Fast Analysis of Time Interval Error in Current-Mode Drivers. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 367-377 (2018) - [j18]Wai-Kong Lee, Ramachandra Achar, Michel S. Nakhla:
Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2518-2529 (2018) - 2017
- [j17]Mina A. Farhan, Michel S. Nakhla, Emad Gad, Ramachandra Achar:
Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 261-270 (2017) - 2014
- [j16]Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla:
Addressing Partitioning Issues in Parallel Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2713-2723 (2014) - 2013
- [c18]Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla:
Efficient parallel scheduler for circuit simulation exploiting binary link formulations. LASCAS 2013: 1-4 - 2012
- [j15]Yinghong Zhou, Emad Gad, Michel S. Nakhla, Ramachandra Achar:
Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 101-108 (2012) - 2011
- [j14]Ramachandra Achar, Michel S. Nakhla, Harjot S. Dhindsa, Arvind R. Sridhar, Douglas Paul, Natalie Nakhla:
Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR). IEEE Trans. Very Large Scale Integr. Syst. 19(2): 319-332 (2011) - 2010
- [j13]Nick Soveiko, Michel S. Nakhla, Ramachandra Achar:
Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 65-77 (2010)
2000 – 2009
- 2009
- [j12]Emad Gad, Michel S. Nakhla, Ramachandra Achar, Yinghong Zhou:
A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1359-1372 (2009) - [j11]Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub:
Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1061-1072 (2009) - 2008
- [j10]Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub:
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 574-578 (2008) - 2007
- [j9]Changzhong Chen, Emad Gad, Natalie Nakhla, Ramachandra Achar:
Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1139-1149 (2007) - [j8]Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. IEEE Trans. Very Large Scale Integr. Syst. 15(1): 48-59 (2007) - [c17]Natalie Nakhla, Michel S. Nakhla, Ramachandra Achar:
Sparse and passive reduction of massively coupled large multiport interconnects. ICCAD 2007: 622-626 - 2006
- [j7]Praveen Pai, Emad Gad, Ramachandra Achar, Michel S. Nakhla, Roni Khazaka:
A Projection-Based Reduction Approach to Computing Sensitivity of Steady-State Response of Nonlinear Circuits. INFORMS J. Comput. 18(2): 173-185 (2006) - [c16]Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. VLSI Design 2006: 667-671 - [c15]Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin:
Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks. VLSI Design 2006: 672-676 - 2005
- [j6]Emad Gad, Changzhong Chen, Michel S. Nakhla, Ramachandra Achar:
Passivity verification in delay-based macromodels of electrical interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2173-2187 (2005) - [j5]Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 819-832 (2005) - [c14]Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis:
Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects. ASP-DAC 2005: 1082-1085 - [c13]Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
On passivity enforcement for macromodels of S-parameter based tabulated subnetworks. ISCAS (4) 2005: 3777-3780 - [c12]Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla:
Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters. ISCAS (6) 2005: 5770-5773 - [c11]Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects. VLSI Design 2005: 629-633 - 2004
- [c10]Natalie Nakhla, Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla:
Fast sensitivity analysis of transmission line networks. ISCAS (5) 2004: 121-124 - [c9]Praveen Pai, Emad Gad, Ramachandra Achar, Roni Khazaka, Michel S. Nakhla:
Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques. ISCAS (5) 2004: 333-336 - 2003
- [c8]Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Passive macromodeling of subnetworks characterized by measured data. ISCAS (3) 2003: 502-505 - 2002
- [c7]Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla:
Passive closed-form time-domain macromodels for on-chip distributed RC interconnects. CICC 2002: 509-512 - 2001
- [j4]Ramachandra Achar, Michel S. Nakhla:
Simulation of high-speed interconnects. Proc. IEEE 89(5): 693-728 (2001) - [j3]Ramachandra Achar, Michel S. Nakhla:
Correction To "simulation of high-speed Interconnects". Proc. IEEE 89(8): 1230 (2001) - [c6]Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla:
A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations. ICECS 2001: 899-902 - 2000
- [j2]Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar:
Simulation of high-speed distributed interconnects using Krylov-space techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 799-808 (2000) - [c5]Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar:
Passive model order reduction of multiport distributed interconnects. DAC 2000: 526-531
1990 – 1999
- 1999
- [c4]Ramachandra Achar, Michel S. Nakhla:
Efficient simulation of on-chip RF components using model-reduction techniques. ISCAS (2) 1999: 81-84 - [c3]Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar:
Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques. ISCAS (6) 1999: 242-245 - [r1]Michel S. Nakhla, Ramachandra Achar:
Interconnect Modeling and Simulation. The VLSI Handbook 1999 - 1998
- [j1]Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang:
Full-wave analysis of high-speed interconnects using complex frequency hopping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 997-1016 (1998) - 1996
- [c2]Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar:
An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. ICCAD 1996: 20-23 - 1995
- [c1]Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang:
Addressing high frequency effects in VLSI interconnects with full wave model and CFH. ICCAD 1995: 53-56
Coauthor Index
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last updated on 2024-11-11 21:30 CET by the dblp team
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