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ORCIDDean L. Lewis
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2010 – 2019
- 2015
[j2]Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015)- 2012
- [b1]Dean L. Lewis:
Design for pre-bond testability in 3D integrated circuits. Georgia Institute of Technology, Atlanta, GA, USA, 2012 - [c9]Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 - 2011
- [j1]Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim:
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 732-745 (2011) - [c8]Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee:
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. ICCD 2011: 90-95 - 2010
- [c7]Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4 - [c6]Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, Hsien-Hsin S. Lee:
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth. HPCA 2010: 1-12
2000 – 2009
- 2009
- [c5]Dean L. Lewis, Hsien-Hsin S. Lee:
Architectural evaluation of 3D stacked RRAM caches. 3DIC 2009: 1-4 - [c4]Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim:
Pre-bond testable low-power clock tree design for 3D stacked ICs. ICCAD 2009: 184-190 - [c3]Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee:
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. ISVLSI 2009: 25-30 - [c2]Dean L. Lewis, Hsien-Hsin S. Lee:
Testing Circuit-Partitioned 3D IC Designs. ISVLSI 2009: 139-144 - 2007
- [c1]Dean L. Lewis, Hsien-Hsin S. Lee:
A scanisland based design enabling prebond testability in die-stacked microprocessors. ITC 2007: 1-8
Coauthor Index
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